Mettle v.0.10.0

Mettle now compiles for the GPU: a native CUDA/PTX backend with kernel and
dispatch syntax. On the CPU, the legacy text-asm backend is gone and nearly every
function now goes through the register-allocating MIR backend. The language gains
function decorators, range-for loops, and @simd vectorization contracts, and the
runtime gets its own native memory allocator.

What's new

• GPU compilation: the compiler emits PTX natively for NVIDIA GPUs. Write
  kernel functions as peers of function, launch them with
  dispatch K[grid, block](args), and index with thread.x, block.x,
  block_dim.x, and grid_dim.x. A new std/gpu module wraps the CUDA Driver
  API. The PTX backend is validated by a ptxas round-trip gate in the test suite
  and differential execution tests on real hardware.
• One backend: the legacy text-asm backend has been removed. The MIR register
  allocator now covers ~97% of functions (up from ~72%), including structs passed
  and returned by value, calls with more than 4 arguments, address-of, switch
  dispatch, and runtime safety checks. Almost no code falls back to
  spill-everything codegen anymore.
• Function decorators: @inline, @noinline, @pure (lets the optimizer
  hoist pure calls out of loops), and @simd / @simd! contracts that verify a
  loop actually vectorized, with diagnostics explaining any bail.
• Range-for syntax: for i in 0..n and inclusive for i in 0..=n.
• Faster integer code: quantized int8 dot products and matmul tiles are
  auto-vectorized with AVX2 (vpmaddwd): 11x over scalar and 3.5x faster than
  gcc -march=native on the dot kernel. Constant division and modulo are
  strength-reduced to magic multiplies, paired div+mod fuse into one division,
  and SIMD kernels now inline into register-allocated functions instead of
  forcing a fallback.
• Native memory subsystem: Mettle's allocator is now written in Mettle
  (std/osmem, std/alloc, std/mem). Build with --native-heap to route
  new/malloc/free through it on Windows and Linux. Double-free and
  invalid-free are detected and rejected.
• Imports: stronger visibility enforcement and selective dependency
  resolution, so only what you import gets compiled in.
• Correctness: the differential fuzzer got new program shapes and automatic
  pass attribution, and found 4 silent miscompiles, all fixed. Also fixed: three
  register-promoted-global bugs exposed by a real GUI program, a uint32
  signedness bug at -O, float32 narrowing bugs, a callee-saved register clobber
  on Win64, and a missing diagnostic for non-void functions without a return.
  Full test suite green throughout.

Full Changelog: v0.9.1...v0.10.0

What's Changed

• Add MIR register allocator, auto-vectorizators, SROA, magic-divide, and modularize SIMD & IR by @marquisburg in #37
• wcs_broadcast_i32_to_ymm emitted legacy movd immediately before a VEX… by @marquisburg in #38
• Native CUDA/PTX backend, full MIR register allocation, and function decorators by @marquisburg in #39

Full Changelog: v0.9.1...v0.10.0