write_verilog emits invalid Verilog (empty/garbled wire names) after -hier flow, is this because it is not fully developed or a bug ?

[sathwikrao0408]

When extracting a Verilog netlist via write_verilog from a design loaded with read_db -hier (hierarchical flow), the output file contains invalid Verilog syntax for some wire declarations. i have read in a genus netlist which does not have any of this.

e.g.:

module DPOPT_INTERNAL_INST_9283 (g66_z,
    g62_z,
    WALLACE_CSA_DUMMY_OP1_Y_WALLACE_CSA_DUMMY_OP_Y_WALLACE_CSA_DUMMY_OP3_out_1,
    mux_viv_s68_235_13_z,
    ADD_UNS_OP4_Y_ADD_UNS_OP2_Y_ADD_UNS_OP_Y_sub_450_58_A);
 input g66_z;
 input g62_z;
 input [11:0] WALLACE_CSA_DUMMY_OP1_Y_WALLACE_CSA_DUMMY_OP_Y_WALLACE_CSA_DUMMY_OP3_out_1;
 input [9:0] mux_viv_s68_235_13_z;
 output [11:0] ADD_UNS_OP4_Y_ADD_UNS_OP2_Y_ADD_UNS_OP_Y_sub_450_58_A;

 wire \^Q ;
 wire \^R ;
 wire \^R ;
 wire \^R ;
 wire \^N ;
 wire \pë<80>X½U ;
 wire ;
 wire n_0;
 wire n_1;
 wire n_15;
 wire n_16;
 wire n_17;
 wire n_18;
 wire n_19;
 wire n_2;
 wire n_20;
 wire n_21;
 wire n_22;
 wire [10:0] wt_mst_irq_offs;
 wire [30:0] wt_msy_base_ad;

the special character based wire definitions are further being used inside the module -

<std_cell> g3096 (.O(n_22),
    .I1(\^N ),
    .I2(g66_z));
 <std_cell> g3097 (.O(n_21),
    .I1(\^Q ),
    .I2(g66_z));
<std_cell> (.O(n_16),
    .I1(\pë<80>X½U ),
    .I2(g66_z));

I would prefer using -heir for my designs, how can i fix this ?

[maliberty]

It is a bug. Can you open an issue with a self-contained test case?