arc-b580-v0.7

• No undocumented IGC builtins left in the SYCL backend: the TernSYCL kernels are moved to upstream main (inline vISA), and the f16 attention DPAS uses inline vISA too. v0.6 still had intel_sub_group_i8_i2_matrix_mad_k32 and _builtin_IB* in the Bonsai path, so this completes the fix for drivers that don't provide them (reported on Lunar Lake / Arc 140V).
• Long n-gram draft checks stay on the XMX attention kernel up to 256 tokens (was 32), with no f16 copy of the KV cache. MTP at long context on the B580: 48K ~73 -> ~76 t/s, 115K ~60 -> ~65 t/s. Accuracy (KLD) unchanged. GGML_SYCL_FA_DEC_DPAS=32 restores the old cap.
• The SYCL backend is built with one device image per kernel (GGML_SYCL_DEVICE_CODE_SPLIT_PER_KERNEL, default ON), so the Xe2 XMX kernels are only compiled when used. This should help GPUs without XMX, but it isn't confirmed yet. The DLL is larger (about 98 MB).

Windows x64 build of the arc-b580 branch for Intel Arc (SYCL). EXPERIMENTAL: built by CI and not yet tested on a
Windows machine. Needs a current Intel Arc driver (an old driver's ze_loader.dll crashes at start).
Unzip, put the model next to it, and run run-bonsai.bat. See README.txt and
docs/bonsai-arc-b580.md. Please report results in https://github.com/Torchit1/llama.cpp/discussions/1