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Feature/axi4 l register interface update#29

Merged
Paebbels merged 6 commits intoVHDL:devfrom
PLC2:feature/AXI4L-register_interface_update
Feb 17, 2026
Merged

Feature/axi4 l register interface update#29
Paebbels merged 6 commits intoVHDL:devfrom
PLC2:feature/AXI4L-register_interface_update

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@stefanunrein
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@stefanunrein stefanunrein commented Nov 23, 2025

New Features

  • Add output port for GitVersionRegister with its register content as records
  • Add missing sources to TerosHDL project file

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@Paebbels

@Paebbels
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Argh. Branch auto-deletion destroyed that PR.

@Paebbels Paebbels reopened this Feb 16, 2026
@Paebbels Paebbels mentioned this pull request Feb 16, 2026
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Minor naming changes.

@stefanunrein
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I applied your suggestions. Are we ready to merge?

@Paebbels Paebbels self-requested a review February 17, 2026 13:28
@Paebbels Paebbels merged commit b513a05 into VHDL:dev Feb 17, 2026
15 of 16 checks passed
@Paebbels Paebbels deleted the feature/AXI4L-register_interface_update branch February 17, 2026 13:29
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2 participants