Add secworks/aes cryptographic engine

[mguthaus]

Design: secworks/aes

Repository: https://github.com/secworks/aes
License: BSD 2-Clause
Language: Verilog
Stars: ~200+

Description

A well-tested, ASIC-proven Verilog implementation of the AES symmetric block cipher (NIST FIPS 197) supporting 128-bit and 256-bit keys. Iterative architecture processing one 128-bit block at a time with 4 S-boxes in the data path.

Why it's a good benchmark candidate

• Industry-relevant: AES is ubiquitous in real chip designs (secure boot, storage encryption, TLS offload). The core has been used in multiple FPGA and ASIC tapeouts.
• New architecture: Cryptographic datapath with S-box lookup tables, key expansion logic, and iterative round processing — a fundamentally different structure from processors, accelerators, and network controllers already in the suite.
• Active development: Maintained by Joachim Strömbergson (secworks), a well-known open-source crypto hardware developer.

Estimated complexity

• Gate count: Small to medium (iterative single-block architecture with 4 S-boxes)
• Memories: Minimal — S-boxes may synthesize as LUTs or small ROMs, no large SRAMs
• IO count: Low (simple bus interface with address, data, read/write, chip select)

Verification

FuseSoC-integrated testbench (tb_aes) with NIST test vectors. Can be simulated with Icarus Verilog or Verilator via FuseSoC. Extensively tested across multiple FPGA and ASIC implementations.

Conversion notes

Pure Verilog 2001 — no conversion needed. Clean, self-contained codebase with no external dependencies.

Target platforms

• asap7
• nangate45
• sky130hd