Upstream update available: designs/src/vortex/dev/repo
| Field |
Value |
| Pinned |
31e4765 (2025-10-19) |
| Upstream |
f00bb14 (2026-04-24) |
| Commits behind |
84 |
| Days stale |
187 |
Severity: MODERATE
The diff is primarily simulation/CI infrastructure with some RTL-adjacent changes:
- RTL/functional changes:
fix srai decode — arithmetic right-shift instruction decode fixrefactor(dtm): relocate debug stack, drop unrelated TF32, add coverage — debug module refactorAdd debug module and JTAG DTM for RISC-V simulation — new debug RTLAdd TF32 support in tensor computation and tracingrename __assert to __vortex_assert — runtime assertion rename
- Build/source restructuring:
simx source tree restructuring for submodules — may affect how RTL is organized for synthesis; ci: fix toolchain scripts for new Verilator + add sta tool
- New integrations: SST (Structural Simulation Toolkit) integration; OpenMPI support; Apptainer CI
- CI: Multiple regression fixes; MPI test coverage; OS support updates (drop Ubuntu 22.04)
- AXI: Fix AXI burst mode from Fixed to INCR for Vivado SmartConnect
Recommendation
Defer. The srai decode fix and source tree restructuring are worth picking up, but the large number of simulation-only additions (SST, OpenMPI, debug server) adds noise. Verify the simx restructuring does not break RTL file paths used in our synthesis flow before updating.
Last refreshed: 2026-04-27T00:00:00Z
Upstream update available: designs/src/vortex/dev/repo
31e4765(2025-10-19)f00bb14(2026-04-24)Severity: MODERATE
The diff is primarily simulation/CI infrastructure with some RTL-adjacent changes:
fix srai decode— arithmetic right-shift instruction decode fixrefactor(dtm): relocate debug stack, drop unrelated TF32, add coverage— debug module refactorAdd debug module and JTAG DTM for RISC-V simulation— new debug RTLAdd TF32 support in tensor computation and tracingrename __assert to __vortex_assert— runtime assertion renamesimx source tree restructuring for submodules— may affect how RTL is organized for synthesis;ci: fix toolchain scripts for new Verilator + add sta toolRecommendation
Defer. The srai decode fix and source tree restructuring are worth picking up, but the large number of simulation-only additions (SST, OpenMPI, debug server) adds noise. Verify the simx restructuring does not break RTL file paths used in our synthesis flow before updating.
Last refreshed: 2026-04-27T00:00:00Z