- Although this project is configured for 115200 baud, you may have to use 120000 baud on your computer to actually interface with the project.
Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.
To learn more and get started, visit https://tinytapeout.com.
- Add your Verilog files to the
srcfolder. - Edit the info.yaml and update information about your project, paying special attention to the
source_filesandtop_moduleproperties. If you are upgrading an existing Tiny Tapeout project, check out our online info.yaml migration tool. - Edit docs/info.md and add a description of your project.
- Adapt the testbench to your design. See test/README.md for more information.
The GitHub action will automatically build the ASIC files using OpenLane.
- FAQ
- Digital design lessons
- Learn how semiconductors work
- Join the community
- Build your design locally
- Submit your design to the next shuttle.
- Edit this README and explain your design, how it works, and how to test it.
- Share your project on your social network of choice:
- LinkedIn #tinytapeout @TinyTapeout
- Mastodon #tinytapeout @matthewvenn
- X (formerly Twitter) #tinytapeout @tinytapeout
-
remember to
wsl --shutdown -
to generate a .vcd, instantiate the virtual python environment
source venv/bin/activateIN WSL and runmake -Bin the test folder -
if starting a new project, open WSL, run
python -m venv venvin the test folder. Then,source venv/bin/activateto start the virtual environment. Then,pip install -r requirements.txtto install the necessary packages. -
start wsl
-
python3 -m venv venv (create virtual environment. MUST BE MADE IN WSL)
-
source venv/bin/activate (activate virtual environment)
-
pip install -r requirements.txt (install necessary packages)
-
change the module name in tb.v
-
make -B (run the testbench)
