DSPi Firmware v1.1.5-beta4
Changes since v1.1.5-beta3:
- New I2S slave clock mode: an external master drives BCK/LRCLK with automatic sample-rate detection and output servo; includes unified/split BCK+LRCLK clock-pin modes and continuous LRCK monitoring that self-heals from framing slips.
- Multiple selectable SPDIF inputs: SPDIF 2 and 3 can be opted in on the shared receiver and switched at runtime.
- Multichannel volume leveller with per-channel detector and apply masks and 5 ms lookahead.
- Per-output loudness compensation with an output-channel mask.
- Per-output-pair multichannel crossfeed.
- IR remote control support with a learn function.
- Control Surfaces v2: button gestures, per-filter/per-channel targets, Hz/Q units, PWM meter LEDs, and per-slot names, with a stage-and-commit Apply/Save/Revert preview.
- More stable clock recovery: the SPDIF output divider is restored to nominal when the clock servo exits.