🚀 Welcome to MMSE_CPP! Road to a Complete End-to-End LTE Baseband Engine

[Wiseung]

Hello everyone, and welcome to the MMSE_CPP community discussions! 👋

Whether you are a DSP engineer, a C++ HPC enthusiast, or a CUDA optimization wizard, we are thrilled to have you here. This discussion board is the place to ask questions, propose architectural changes, share benchmarking results, and coordinate our development efforts.

🌟 What is MMSE_CPP?

MMSE_CPP is a high-performance, heterogeneous LTE Physical Layer (PHY) baseband engine. We leverage C++ AVX2/AVX-512 for ultra-low latency control plane tasks and NVIDIA CUDA streams for massive throughput data plane equalization.

🏗️ Where We Are Now

Thanks to the hard work so far, we have built a very robust "muscle" for the baseband receiver. Currently, the engine successfully handles:

• Strict SoA (Structure of Arrays) memory layouts for zero-copy SIMD processing.
• CRS-based Channel Estimation & Noise Variance ($\sigma^2$) tracking.
• PDSCH 2x2 MIMO MMSE Equalization with Cramer's rule SIMD expansion.
• PCFICH Extraction and CFI block decoding.
• PDCCH SFBC Demapping (Transmit Diversity without matrix inversion).

🧩 The Missing Pieces (Call for Contributors!)

While our equalizers are fast, we need to build the "brain" and the "glue" to connect our physical layer engine to the L2 MAC layer. To achieve a fully functioning end-to-end L1 receiver, we are actively looking for contributors to help tackle the following modules:

1. PDCCH Blind Decoding (Control Plane): We need to implement CCE De-interleaving and a Wrap-Around Viterbi Algorithm (WAVA) to extract the DCI payload and verify the RNTI CRC.
2. Rate Dematching & HARQ (Memory-Bound): Building the circular buffer reconstruction logic to untangle the punctured/repeated soft bits and combine them with previous HARQ failures.
3. Soft Demapper: Converting the Equalizer output (x_hat and sinr) into QPSK, 16QAM, and 64QAM Log-Likelihood Ratios (LLRs).
4. Scrambling/Descrambling: Fusing the Gold-sequence pseudo-random descrambling directly into our AVX2/CUDA kernels for zero-cost execution.

💬 Let's Discuss!

We want to hear your thoughts on how to architecture the next steps:

• Should we implement the Viterbi Decoder on the CPU to avoid PCIe latency, or batch multiple candidates on the GPU?
• What are your favorite open-source FEC libraries (Turbo/LDPC) that we could interface with?

📌 Useful Links

Before diving into the code, check out our newly established resources:

• 📖 Project Wiki (Read about our SoA memory model and Heterogeneous Dispatch architecture).
• 📋 Project Roadmap / Board (Pick up a task from the backlog!).
• 🛡️ Security Policy.

Feel free to introduce yourself below, share what you're working on, or just say hi. Let's build the ultimate open-source baseband engine together! 🚀