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lib: sbi: Enable Ssqosid Ext using mstateen0#5

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cp0613 merged 1 commit intoXUANTIE-RV:opensbi-v1.7-devfrom
cp0613:opensbi-v1.7-dev
Apr 1, 2026
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lib: sbi: Enable Ssqosid Ext using mstateen0#5
cp0613 merged 1 commit intoXUANTIE-RV:opensbi-v1.7-devfrom
cp0613:opensbi-v1.7-dev

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@cp0613 cp0613 commented Apr 1, 2026

The QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers.

If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception.

This extension can be found in the RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual

Changes in v5:

  • Remove SBI_HART_EXT_SSQOSID dependency SBI_HART_PRIV_VER_1_12

Changes in v4:

  • Remove extraneous parentheses around SMSTATEEN0_SRMCFG

Changes in v3:

  • Check SBI_HART_EXT_SSQOSID when swapping SRMCFG

Changes in v2:

  • Remove trap-n-detect
  • Context switch CSR_SRMCFG

Reviewed-by: Radim Krčmář rkrcmar@ventanamicro.com
Link: https://lore.kernel.org/r/20251114115722.1831-1-cp0613@linux.alibaba.com

The QoS Identifiers extension (Ssqosid) introduces the srmcfg register,
which configures a hart with two identifiers: a Resource Control ID
(RCID) and a Monitoring Counter ID (MCID). These identifiers accompany
each request issued by the hart to shared resource controllers.

If extension Smstateen is implemented together with Ssqosid, then
Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. If
mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less
privileged than M-mode raise an illegal-instruction exception. If
mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented,
attempts to access srmcfg when V=1 raise a virtual-instruction exception.

This extension can be found in the RISC-V Instruction Set Manual:
https://github.com/riscv/riscv-isa-manual

Changes in v5:
 - Remove SBI_HART_EXT_SSQOSID dependency SBI_HART_PRIV_VER_1_12

Changes in v4:
 - Remove extraneous parentheses around SMSTATEEN0_SRMCFG

Changes in v3:
 - Check SBI_HART_EXT_SSQOSID when swapping SRMCFG

Changes in v2:
 - Remove trap-n-detect
 - Context switch CSR_SRMCFG

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com>
Link: https://lore.kernel.org/r/20251114115722.1831-1-cp0613@linux.alibaba.com
Signed-off-by: Anup Patel <anup@brainfault.org>
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github-actions bot commented Apr 1, 2026

We have mailing list based patch review so it would be great if you can send these patchs to OpenSBI mailing list.

You need to join OpenSBI mailing list using following link
http://lists.infradead.org/mailman/listinfo/opensbi

Make sure you use "git send-email" to send the patches.

Thanks for your contribution to OpenSBI project.

@github-actions github-actions bot closed this Apr 1, 2026
@github-actions github-actions bot locked and limited conversation to collaborators Apr 1, 2026
@cp0613 cp0613 reopened this Apr 1, 2026
@cp0613 cp0613 merged commit ec52ac7 into XUANTIE-RV:opensbi-v1.7-dev Apr 1, 2026
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