v1.4.0

🧠 TL;DR

✅ Major expansion of dynamic runtime sequences for expressive host-driven execution
✅ New HRX (amdxdna) Host Runtime backend and improved full-ELF deployment workflows
✅ Faster IRON execution with optional kernel inlining and improved JIT infrastructure
✅ Stronger compiler verification, ObjectFIFO analysis, and DMA correctness
✅ Continued compiler modernization, documentation, and Windows support

Dynamic runtime sequences take a major step forward in this release, enabling significantly more expressive host-controlled execution.

Added dynamic SSA-based runtime sequence operands, dynamic DMA descriptors, runtime BD allocation, dynamic conditionals, and runtime tracing support → @hunhoffe
Added C++ TXN generation, dynamic BD-word encoding, an equivalence test harness validating static and dynamic execution, and an example fully dynamic multi-column GEMM with runtime-configurable problem sizes → @hunhoffe, @jgmelber
Added new runtime-sequence operations including DMA channel reset, DMA channel reset loops, and core reset support → @atassis

Introduced the new HRX (amdxdna) Host Runtime backend, enabling XRT-free deployment and xclbin packaging → @Abhishek-Varma
Added optional kernel inlining for ExternalFunction, allowing C++ kernels to be linked directly into aie.core instead of being invoked via func.call, reducing call overhead and improving tight-loop performance by up to 2× → @fifield
Added full-ELF support to iron.jit and XRTHostRuntime, exposing generated PDI artifacts and improving host-driven deployment workflows → @hunhoffe
Added support for pinning L1 buffers and ObjectFIFO DMA channels for host-driven applications → @hunhoffe
Enabled dynamic lock acquisition inside ObjectFIFO acquire/release operations and added support for control-packet-based device configuration as a drop-in alternative to load_pdi → @andrej

Added support for more than five host buffers in aiecc, removing a long-standing full-ELF limitation and fixing associated segmentation faults → @hunhoffe, @erwei-xilinx
Introduced a declarative rewrite of aiecc, parallel execution infrastructure, and declarative simulation flows to improve maintainability and compilation performance → @andrej
Improved compiler scalability, routing performance, memory placement, and JIT cache correctness through numerous infrastructure improvements → @atassis, @jgmelber, @w3lld1

Compiler diagnostics and verification have been substantially strengthened, allowing more invalid programs to be detected before deployment.

Added verification for DMA buffer descriptor limits, runtime-sequence deadlocks, DMA channel reset correctness, ObjectFIFO liveness, and placement-related failures → @atassis, @hunhoffe, @xhmelon
Improved diagnostics for unplaced tiles and strengthened validation throughout the lowering pipeline → @atassis, @hunhoffe
Improved correctness across AIE2 kernels, routing, JIT execution, and runtime behavior through numerous bug fixes from multiple contributors

Published HostRuntime Python API documentation and comprehensive runtime-sequence references → @ColumbusLabs, @atassis
Added Agentic Programming documentation, refreshed the project roadmap, expanded community pages, and improved website organization → @hunhoffe, @erwei-xilinx
Improved Windows installation, setup scripts, and added Windows CI support for Ryzen AI development → @thomthehound, @jgmelber
Expanded the IRON programming skill chain, refreshed programming examples, and improved developer documentation throughout the project → @hunhoffe, @thomthehound

Removed legacy ADF infrastructure, deprecated AIE1/Chess tutorials, obsolete runtime support, and other unmaintained components → @hunhoffe, @jgmelber
Continued migration to upstream Xilinx and ROCm repositories for core dependencies and toolchains → @jgmelber
Modernized CI with improved retry logic, dependency management, wheel validation, cache efficiency, and reliability across supported platforms → @hunhoffe, @andrej, @atassis

This release includes several programming model updates that may require downstream projects to be updated.

Dynamic runtime sequences now use SSA operands throughout the compiler. Runtime sequence scalar values and DMA descriptor fields (sizes, strides, offsets, and lengths) have transitioned from attributes toward SSA values as part of the dynamic runtime sequence infrastructure.
The IRON Runtime has been reworked around an eager callback execution model. Existing Python runtime sequence generation code may require updates to match the new execution model.
TileDMA packet headers are now represented as explicit dma_bd_packet operations rather than attributes, improving compiler analysis and verification.
Compiler verification is stricter. Programs with invalid ObjectFIFO usage, DMA configuration, runtime-sequence behavior, or placement issues that previously compiled may now produce diagnostic errors instead.

Development continues in several areas that are expected to evolve over upcoming releases:

Continued consolidation of DMA lowering and verification may introduce API refinements to npu.dma_memcpy_nd.
ObjectFIFO APIs and lowering will continue evolving as part of ongoing restructuring efforts.
The IRON Python APIs will continue expanding to make dynamic runtime sequence generation more expressive, ergonomic, and host-centric.
Native Windows development experience improvements, CI enhancements, build infrastructure, deprecation of WSL-based build processes.

A warm welcome to our first-time contributors!

Thank you to everyone who contributed to the v1.4.0 release!