v1.4.1

v1.4.1

🧠 TL;DR

• ✅ Expanded HostRuntime with NpuTensor, sub-region views, and explicit storage
• ✅ Peano is now the default AIE core backend, with improved LLVM compatibility
• ✅ More robust IRON kernel inlining, JIT caching, and host-runtime infrastructure
• ✅ Improved tracing, routing, DMA correctness, and compiler diagnostics
• ✅ Stronger Windows support, CI coverage, and Python developer tooling

🔍 Highlights

🧩 IRON & Host Runtime

• Expanded the Python HostRuntime with NpuTensor, sub-region views, and explicit Storage, providing a richer foundation for host-side NPU memory management → @atassis
• Improved IRON external-kernel inlining by merging LLVM IR in-process before Peano downgrade, making the inline compilation path introduced in v1.4 more robust → @fifield
• Strengthened JIT cache correctness by validating recorded dependency manifests, ensuring cached artifacts are invalidated when their compilation dependencies change → @atassis
• Unified HRX and XRT hardware test infrastructure around a runtime-agnostic NPU test suite → @Abhishek-Varma
• Fixed Windows XRTKernelResult.run NPU timing precision → @astrelsky

⚙️ Compiler & Peano

• Peano is now the default core backend in aiecc, continuing the transition away from Chess for standard compilation flows → @atassis
• Improved Peano compatibility following the LLVM 24 transition, including narrow-float literal handling, arithmetic min/max lowering, and preservation of module alignment → @erwei-xilinx
• Fixed legal start-column selection for virtualized NPU partitions and improved column-control overlay generation → @atassis
• Moved additional device-specific behavior, including default core stack size, into AIETargetModel and strengthened handling of invalid target devices → @atassis
• Improved build diagnostics by validating Peano installation paths and backend directories early instead of failing later in compilation → @atassis

🛡️ DMA, Routing & Correctness

• Improved DMA robustness with safer verification of BD dimensions, target-aware reset register resolution, and better handling of unplaced tiles → @atassis
• Wired DMA pad_value through to hardware and moved its representation to the DMA channel → @jskimko
• Fixed packet-flow channel sharing and now fail compilation when packet-flow routing is incomplete → @andrej, @jskimko
• Added hardware coverage for routing multiple flows with the same packet ID → @erwei-xilinx
• Fixed AIEVec signedness handling through vector.contract lowering, including consistent semantics for signless matmul operands → @erwei-xilinx
• Fixed runtime ELF loading to correctly zero the p_memsz - p_filesz region of PT_LOAD segments → @hunhoffe

📡 Tracing & AIE2P

• Added core EVENT_PC tracing mode for program-counter-based event tracing → @FIM43-Redeye
• Improved core-memory event activation when tracing individual tiles → @atassis
• Expanded trace coverage for bf16 single-core matmul configurations → @hunhoffe
• Added an AIE2P matrix-multiply activation epilogue supporting three RTP-selected GEMM epilogues from a single xclbin → @atassis

🪟 Windows, Build & CI

• Expanded Windows CI to build from wheels and smoke-test produced packages, with Peano nightlies now required to provide wheels for every supported CI platform → @jgmelber
• Improved build scalability with configurable parallelism and more reliable ccache integration → @jskimko, @atassis
• Improved on-device CI reliability and throughput through finer-grained device locking, targeted transient-failure retries, and reduced redundant NPU testing → @atassis, @jgmelber
• Added diff coverage reporting, PR-time documentation validation, and broader wheel/test coverage to catch regressions earlier → @hunhoffe
• Moved GitHub-hosted CI away from the deprecated Ubuntu 22.04 runner image → @hunhoffe

🛠️ Developer Experience

• Added Ruff linting and expanded Ruff/Pyright coverage across programming examples, including consistent docstring-style enforcement → @hunhoffe
• Improved test metadata by explicitly identifying each test's backend and moving tests away from Chess where it is no longer required → @atassis
• Improved documentation deployment reliability and added the ROCm-NPU Discord channel to the project documentation → @hunhoffe

⚠️ Migration Notes

This release continues several transitions introduced in v1.4.0. Most users should be able to upgrade without major changes, but downstream projects should be aware of the following:

• Peano is now the default AIE core backend in aiecc. Workflows that implicitly relied on Chess should explicitly select the required backend or migrate to Peano where possible.
• Target validation is stricter. Requests for unknown AIEDevice values now produce an error instead of silently falling back to the VC1902 target model.
• Packet-flow routing is more strictly validated. Incomplete packet-flow routing now fails compilation instead of allowing an incomplete configuration to proceed.
• DMA verification is stricter. Malformed or inconsistent DMA BD dimension lists that may previously have progressed further through compilation are now diagnosed earlier.

🔭 Looking Ahead

Several programming-model areas remain under active development and may continue to evolve in upcoming releases:

• Continued consolidation of DMA lowering and verification may introduce API changes or deprecation around npu.dma_memcpy_nd.
• ObjectFIFO APIs and lowering are expected to evolve as part of ongoing ObjectFIFO restructuring.
• The IRON Python APIs will continue expanding toward more ergonomic, dynamic runtime-sequence generation and host-driven execution.

🙌 New Contributors

A warm welcome to our first-time contributor!

• @astrelsky

Thank you to everyone who contributed to the v1.4.1 release!