GitHub - Zanatticus/RISC-V-Processor: A RISC-V processor created from scratch with SystemVerilog with a complimentary assembly instruction converter · GitHub

Name		Name	Last commit message	Last commit date
Final-RISC-V-Computer.png		Final-RISC-V-Computer.png
Lab7Prelab.asm		Lab7Prelab.asm
adaptor_display.sv		adaptor_display.sv
alu_instrmem_top.sv		alu_instrmem_top.sv
converter.py		converter.py
debounce.sv		debounce.sv
execute.sh		execute.sh
instruction_decoder.sv		instruction_decoder.sv
lab_7_constraint.xdc		lab_7_constraint.xdc
mapper.sv		mapper.sv
program_counter.sv		program_counter.sv
regfile.sv		regfile.sv

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A RISC-V processor created from scratch with SystemVerilog with a complimentary assembly instruction converter

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