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1. rv32i-pipelined rv32i-pipelined Public

   A 5-stage pipelined RV32I RISC-V processor in Verilog featuring data forwarding, load-use hazard detection with stalling, and static branch prediction with pipeline flushing.

   Verilog

2. ttc-project ttc-project Public

   Developing supporting resources for Team Anant's 1U communication system, including HFSS-based turnstile antenna simulations, MATLAB link budget analysis, and Arduino code for LoRa beacon packetiza…

   C++