v0.2.4

• Added generation-safe typed JIT-to-JIT calls for context-free Word/Float64 targets in straight-line and CFG IR.
• Added atomic target-table publication, exact compiled-generation leases, cache-safe invalidation, and concurrent fast-call retargeting.
• Added a strict 128-bit SIMD semantic core with six data vectors, canonical masks, lane operations, comparisons, selection, shuffles, and widening.
• Extended straight-line and CFG SSA, verification, interpretation, optimization, allocation, spill handling, and edge copies for vector values.
• Added complete AArch64 NEON lowering for the delivered SIMD surface, including bounded I64x2 multiplication legalization.
• Added complete x86-64 SSE2 lowering for System V and Windows, including aligned spills and bounded scalar legalization.
• Added bounded RV64IMD scalar SIMD lowering without requiring or claiming RVV.
• Added bounded aligned and unaligned 128-bit vector memory with explicit per-lane byte order and failure-atomic transfers.
• Added target-profile capability preflight and compiled lowering telemetry without code emission.
• Added bounded generated-code atomics with explicit memory orders, target-selected native paths, fallbacks, and litmus qualification.
• Added function-owned non-executable patch cells with release/acquire publication, CAS, fetch-add, and cache-generation lifetime.
• Added retained SIMD, patch-cell, and fast-call performance gates plus sanitizer, stress, package, and real-host qualification.