An educational CPU simulator and assembler designed for first-semester computer architecture courses at Universität Trier. CPYU-V16 implements a minimal 16-bit RISC architecture with Harvard memory model, making it ideal for teaching fundamental concepts in computer organization.
- 16-bit word-addressed architecture with 32 general-purpose registers
- Harvard architecture model with separate program and data memory
- 64 Ki × 16-bit word memory (65,536 words)
- Two-pass assembler with label support
- Real-time debugging with single-step execution
- Comprehensive error handling for educational feedback
- Built-in self-test suite for validation
- Registers: 32 general-purpose registers (
r0-r31)r0is hard-wired to zero (writes ignored)
- Memory: 64K words of 16-bit memory (word-addressed 0-65535)
- Immediate Values: Range from -32768 to 65535 (masked to 16-bit)
- Arithmetic: All operations wrap around at 16 bits (mod 2¹⁶)
- Arithmetic & Logic:
ADD,ADDI,SUB,AND,OR,XOR - Memory Access:
LD,ST(absolute addressing) - Control Flow:
BEQ,BNE,JMP,HALT - I/O:
IN(stdin),OUT(formatted stdout) - Pseudo-instructions:
LI(load immediate),MOV(register copy)
- Python 3.7 or higher
- No additional dependencies required
git clone <repository-url>
cd cpyu# Run an assembly program
python cpyu.py sumup_n.cpyu
# Run with single-step debugging
python cpyu.py --single-step sumup_n.cpyu
# Run built-in self-tests
python cpyu.py --selftest; Simple addition example
LI r1, 10 ; Load immediate 10 into r1
LI r2, 20 ; Load immediate 20 into r2
ADD r3, r1, r2 ; r3 = r1 + r2
OUT r3 ; Print result: +00030 (0x001e)
HALT; Read a number and double it
IN r1 ; Read integer from stdin
ADD r2, r1, r1 ; r2 = r1 + r1 (double)
OUT r2 ; Print doubled value
HALT; Store and load from memory
LI r1, 0x00FF ; Load value
ST r1, 100 ; Store at memory address 100
LD r2, 100 ; Load from memory address 100
OUT r2 ; Print loaded value
HALT- Comments: Lines starting with
;or# - Labels: Identifiers followed by
:(used for branches/jumps) - Instructions: Mnemonic followed by operands
- Operands: Separated by commas or spaces
- Decimal:
42,-15 - Hexadecimal:
0x2A,-0x000F
- Registers:
r0throughr31(case-insensitive) r0always contains zero
python cpyu.py [options] <assembly_file>
Options:
--single-step Enable single-step debugging mode
--selftest Run comprehensive self-tests
-h, --help Show help messageUse --single-step to trace execution:
python cpyu.py --single-step sumup_n.cpyuOutput shows:
PC=00001 LI r1, 1 | r1=0001
PC=00002 LI r3, 0 | r3=0000
PC=00003 ADD r3, r3, r1 | r3=0001
...
The simulator provides detailed error messages for:
- Memory errors: Out-of-bounds access
- Input errors: Invalid or out-of-range values
- Assembly errors: Invalid syntax, unknown opcodes
- Runtime errors: Execution problems
cpyu/
├── cpyu.py # Main simulator and assembler
├── cpyu_isa.md # Complete instruction set documentation
├── sumup_n.cpyu # Example program (sum of 1 to N)
├── README.md # This file
└── WARP.md # Development guidelines
Run the comprehensive self-test suite:
python cpyu.py --selftestTests cover:
- Arithmetic operations and overflow handling
- Memory load/store operations
- Control flow (branches, jumps)
- I/O operations
- Error conditions
CPYU-V16 is designed specifically for computer architecture education:
- Minimal complexity allows focus on fundamental concepts
- Clear instruction semantics with predictable behavior
- Debugging support helps students understand execution flow
- Comprehensive error checking provides immediate feedback
- Harvard model clearly separates code and data
For complete instruction set documentation and architectural specifications, see cpyu_isa.md.
Key architectural features:
- Word-addressed memory (not byte-addressed)
- No pipeline or cache complexity
- Single-cycle instruction execution model
- Explicit register-to-register operations
- Immediate values handled consistently across instructions
This is an educational project developed at Universität Trier. For development guidelines and project structure information, see WARP.md.
Educational use license. Developed for computer architecture courses at Universität Trier.
CPYU-V16 v1 — Universität Trier, 2025