ISA Reference

RR16X Instruction Semantics Common execution model

For every instruction:

CPU fetches instruction word from: ProgramEAM:PC Decode instruction. Fetch encoded immediates, if present: Immediate X Immediate Y

in that order.

Execute instruction. Increment PC. PC = PC + instruction_length

Note:

PC increment occurs after execution. Branches and jumps modify PC during execution; final PC increment behavior must be resolved per instruction. Undefined opcodes execute as NIL. Immediate fetch happens before any EAM modification caused by the instruction. Instruction Classes ALU Instructions

Format:

OP Rd, Rx, Ry

or

OP Rd, Rx, Imm

Registers:

Rd = destination Rx/Ry = sources

No flags are modified.

ADD

Opcode:

0x1000

Semantics:

Rd = Rx + Ry

or

Rd = Rx + Imm

Overflow:

ignored wraps modulo 65536 SUB

Opcode:

0x2000

Semantics:

Rd = Rx - Ry

or

Rd = Rx - Imm

No flags.

AND

Opcode:

0x3000 Rd = Rx & Ry OR

Opcode:

0x4000 Rd = Rx | Ry NOT

Opcode:

0x5000 Rd = ~Rx XOR

Opcode:

0x6000 Rd = Rx ^ Ry SHL

Opcode:

0x7000 Rd = Rx << amount

Shift amount:

lower 4 bits of operand

Result:

16-bit wrap SHR

Opcode:

0x8000 Rd = Rx >> amount

Logical shift.

Memory Instructions LDM

Opcode:

0x9000

Format:

LDM Rd, Address

Semantics:

Effective address:

EA = DataEAM:Address

Read:

Rd = Memory[EA] Address calculation occurs before any architectural state modification.

The third operand is ignored and may be omitted.

If the resolved address maps to:

• RAM: normal memory read
• ROM: normal memory read
• Peripheral: peripheral read transaction

Peripheral reads may have device-defined side effects

STM

Opcode:

0xA000

Format:

STM Address, Rx

Semantics:

Memory[DataEAM:Address] = Rx Address may be:

• immediate
• register-derived

The source value is taken from the specified value register.

Operation order:

1. Calculate destination address.
2. Obtain source value.
3. Perform bus write.

Writes:

• RAM: stored normally
• ROM: ignored
• Peripheral: forwarded to peripheral device

Peripheral writes may have device-defined side effects.

Jump Register Instructions STJ

Opcode:

0xB000

Semantics:

JR = immediate address

Only JR changes.

Does not modify PC.

Does not consume JR.

Branch Instructions

No flags exist.

Branches directly compare operands.

Signed comparison

Example:

JLT address, Rx, Ry

Semantics:

if ((int16_t)Rx < (int16_t)Ry) PC = JR OTHER COMPARISONS AVAILABLE: JEQ (==) JLE (<=) JGT (>) JNE (!=) JGE (>=) JMP (unconditional) Otherwise:

PC continues normally Unsigned comparison

Example:

JLT.U

Uses:

(uint16_t)

comparison. OTHER UNSIGNED COMPARISONS AVAILABLE: JEQ.U JLE.U JGT.U JNE.U JGE.U Jump JMP

Opcode:

0xC700

Semantics:

PC = JR

JR unchanged.

Call CAL

Opcode:

0xD000 The hardware call stack is to have no less than 256 entries. Semantics:

Push:

(ProgramEAM << 16) | PC_after_increment

onto hardware call stack.

Then:

PC = target

Bank handling:

Assembler inserts EAM changes as required.

Return RET

Opcode:

0xE000

Semantics:

Pop:

return_address

Restore:

ProgramEAM = return_address >> 16 PC = return_address & 0xFFFF

RET also enables interrupts.

RET.C

Opcode:

0xE800

Semantics:

Same return behavior as RET.

Additionally:

InterruptEnable = false Halt HLT

Opcode:

0xF000

CPU enters halted state.

Wake behavior:

Implementation-defined.

NIL

Opcode:

0xC000

Semantics:

No operation.

However:

May consume encoded immediates. Maximum: Immediate X Immediate Y