RR16X MEMORY MODEL

ADDRESS BUS WIDTH: Logical address width: 32 bits Implemented address width: 27 bits by default [26:16] BANK // [31:16] as a 32-bit address space [15:0] OFFSET HighBits:LowBits ProgramEAM:PC and DataEAM:Address each form one address.

DATA BUS WIDTH: 16 bits [15:0] Data

RAM SIZE: By default, 256 MiB (268,435,456 bytes) w/ 16-bit word granularity could be expanded to 8 GiB (8,589,934,592 bytes) w/ 16-bit word granularity (Requires 32-bit address space expansion)

0x0000:0000 - 0x07FF:FFFF - GENERAL MEMORY (DEFAULT) 0x07FF:0000 - 0x07FF:FFFF - EXTENSION/CRITICAL SPACE (See ABI)

ROM behavior: ROM behavior is implementation-defined until ROM hardware is introduced. Unmapped reads: Return 0x0000

Unmapped writes: Do nothing.

Peripheral priority: As address collisions on peripherals is unsupported, this is unnecessary. Peripheral address regions must not overlap. Behavior is undefined if multiple peripherals claim the same address.

Alignment: No such concept exists on the RR16X. Every address refers to one 16-bit word. Bytes are a foreign concept on the RR16X.

Bank wrapping: Offset overflow increments the bank.

Full address overflow wraps modulo 2^(implemented width)

Example:

FFFF:FFFF + 1 = 0000:0000

PERIPHERAL ADDRESS STUFF Bus Access Types

The bus supports:

Read

Source requests:

read(address)

Result:

uint16_t data Write

Source provides:

write(address,value)

No return value.

ddress Decode Order

The bus resolves accesses in this order:

Peripheral address ranges RAM region ROM region Unmapped behavior

Peripheral Access

Peripherals advertise:

readableAddresses writableAddresses

The bus checks these lists.

If an address is claimed:

Read

The owning peripheral receives:

read(address) Write

The owning peripheral receives:

write(address,value)

Peripheral Rules: Peripheral addresses must not overlap. Multiple peripherals claiming the same address is unsupported. Behavior is undefined if collisions occur. There is no peripheral priority system. APList order does not define address priority.

APList order only defines:

tick() order

Interrupt Enhancer Mk.2 (AKA InterruptEnhancer)

The InterruptEnhancer is memory mapped.

Address: 0x07FF'FFF4 - Status register (read only) 0x07FF'FFF5 - Mask register (read/write)

Status register:

• Each bit represents one interrupt channel.
• Bit N = 1 indicates interrupt channel N is currently pending.
• Bit N = 0 indicates interrupt channel N is inactive.

Mask register:

• Each bit controls whether interrupt channel N participates in CPU interrupt arbitration.
• Bit N = 1 enables channel N.
• Bit N = 0 disables channel N.

The mask register does not clear pending interrupts.

DMA Controller

DMA registers:

Address              Register
--------------------------------------------------
0x07FF'FFEE          Destination address high bits
0x07FF'FFEF          Source address high bits
0x07FF'FFF0          No. Of words to move <- Runs DMA while this address != 0 
0x07FF'FFF1          Destination address low bits
0x07FF'FFF2          Source address low bits

DMA Will raise an interrupt immediately prior to completion. Also, if DMA writes/reads to a memory-mapped device register, it WILL trigger that device's functionality. This includes DMA itself. Do with this what you will. EXACT ORDERING:

DMA tick:

1. Detect final transfer
2. Raise interrupt
3. Transfer final word
4. Finish

DMA Can transfer memory between any two locations in memory.