ISA Reference

RR16X Instruction Semantics Common execution model

For every instruction:

CPU fetches instruction word from: ProgramEAM:PC Decode instruction. Fetch encoded immediates, if present: Immediate X Immediate Y

in that order.

Execute instruction. Increment PC. PC = PC + instruction_length

Note:

PC increment occurs after execution. Branches and jumps modify PC during execution; final PC increment behavior must be resolved per instruction. In the case of a branch succeeding, or a subroutine call/return, normal PC increment is suppressed. On stack overflow/underflow, system may have an implementation-defined behavior If a conditional branch is not taken, PC is incremented by the instruction length normally. Undefined opcodes execute as NIL. Immediate fetch happens before any EAM modification caused by the instruction. NOTE: Any Rx, Ry may be substituted for an immediate. So (Rx, Ry) (Rx, imm), (imm,Ry) (imm,imm) are all allowed. Instruction Classes ALU Instructions

Format:

OP Rd, Rx, Ry

or

OP Rd, Rx, Imm

Registers:

Rd = destination Rx/Ry = sources

No flags are modified. EAM.SET OPCODE 0x0000 Semantics: DATA EAM = Rx

IVR.SET OPCODE 0x0800 Semantics: Interrupt Vector Register = Rx

ADD

Opcode:

0x1000

Semantics:

Rd = Rx + Ry

If the M flag is enabled, 1 is added to the sum Overflow:

ignored wraps modulo 65536 SUB

Opcode:

0x2000

Semantics:

Rd = Rx - Ry if the M flag is enabled, 1 is subtracted from the result No flags.

AND

Opcode:

0x3000 Rd = Rx & Ry If the M flag is enabled, Ry is inverted OR

Opcode:

0x4000 Rd = Rx | Ry If the M flag is enabled, Ry is inverted NOT

Opcode:

0x5000 Rd = ~Rx If the M flag is enabled, NOT acts as a bitwise two's complement negation XOR

Opcode:

0x6000 Rd = Rx ^ Ry If the M flag is enabled, Ry is inverted SHL

Opcode:

0x7000 Rd = Rx << amount

Shift amount:

lower 4 bits of operand

Result:

16-bit wrap

If the M flag is enabled, it becomes a rotate left SHR

Opcode:

0x8000 Rd = Rx >> amount

Logical shift. If the M flag is enabled, it becomes a rotate right Memory Instructions LDM

Opcode:

0x9000

Format:

LDM Rd, Address If the M flag is enabled, and address is a register, the address register will be post-incremented (incremented AFTER memory read) Semantics:

Effective address:

EA = DataEAM:Address

Read:

Rd = Memory[EA] Address calculation occurs before any architectural state modification.

The third operand is ignored and may be omitted.

If the resolved address maps to:

• RAM: normal memory read
• ROM: normal memory read
• Peripheral: peripheral read transaction

Peripheral reads may have device-defined side effects

STM

Opcode:

0xA000

Format:

STM Address, Rx

Semantics:

Memory[DataEAM:Address] = Rx Address may be:

• immediate
• register-derived

The source value is taken from the specified value register.

Operation order:

1. Calculate destination address.
2. Obtain source value.
3. Perform bus write.

Writes:

• RAM: stored normally
• ROM: ignored
• Peripheral: forwarded to peripheral device

Peripheral writes may have device-defined side effects. If the M flag is enabled, and Address is a register, the address register is post-incremented ( incremented AFTER memory write) Jump Register Instructions STJ

Opcode:

0xB000

Semantics:

JR = Rx

Only JR changes.

Does not modify PC.

Does not consume JR. If the M flag is enabled, Only the low 16 bits of the jump register is written Branch Instructions

No flags exist.

Branches directly compare operands. The M flag is treated as the high bit of the condition (second highest) nibble Signed comparison

Example:

JLT Rx, Ry (C1XY)

Semantics:

if ((int16_t)Rx < (int16_t)Ry) PC = JR OTHER COMPARISONS AVAILABLE (ALL SIGNED, ALL PERFORM THE SAME OPERATION (APART FROM PERFORMING THEIR RESPECTIVE COMPARISON)): JEQ (==) (C2XY) JLE (<=) (C3XY) JGT (>) (C4XY) JNE (!=) (C5XY) JGE (>=) (C6XY) JMP (unconditional) (C700) Otherwise:

PC continues normally Unsigned comparison

Example:

JLT.U Rx Ry (C8XY)

Uses:

(uint16_t)

comparison. OTHER UNSIGNED COMPARISONS AVAILABLE (ALL UNSIGNED, SAME BEHAVIOR AS SIGNED COUNTERPART, BUT IGNORES SIGN (INTERPRETS OPERANDS AS uint16_t)): JEQ.U (C9XY) JLE.U (CAXY) JGT.U (CBXY) JNE.U (CCXY) JGE.U (CDXY) CE and CF are unused. Jump JMP

Opcode:

0xC700

Semantics:

PC = JR

JR unchanged.

Call CAL

Opcode:

0xD000 The hardware call stack is to have no less than 256 entries. Semantics:

Push:

(ProgramEAM << 16) | PC_after_increment PC_after_increment = PC + LX + LY + 1 onto hardware call stack.

Then:

PC = target ( Supplied from given operand) WILL MODIFY ProgramEAM (Though CAL.C won't) If the M flag is disabled, the program EAM will not change Bank handling:

Assembler inserts EAM changes as required.

Return RET

Opcode:

0xE000

Semantics:

Pop:

return_address

Restore:

ProgramEAM = return_address >> 16 PC = return_address & 0xFFFF

RET also enables interrupts.

RET.C

Opcode:

0xE800

Semantics:

Pop: return_address

Restore: ProgramEAM = return_address >> 16 PC = return_address & 0xFFFF

InterruptEnable = false Halt HLT

Opcode:

0xF000

CPU enters halted state.

Wake behavior:

Implementation-defined.

NIL

Opcode:

0xC000

Semantics:

No operation.

However:

May consume encoded immediates. Maximum: Immediate X Immediate Y