Refactor CPU feature detection to use an explicit x86 whitelist#258
Refactor CPU feature detection to use an explicit x86 whitelist#258ihb2032 wants to merge 16 commits intoalibaba:mainfrom
Conversation
There was a problem hiding this comment.
Your free trial has ended. If you'd like to continue receiving code reviews, you can add a payment method here.
2192b65 to
061258b
Compare
061258b to
5d725df
Compare
5d725df to
6040065
Compare
|
@ihb2032 please take a look at this error: https://github.com/alibaba/zvec/actions/runs/24500696519/job/71607486150 Seems the ci job can be brought up after Github App was setup. Any problem, let me know. |
|
Hi @richyreachy, thanks for pointing that out! I checked the logs and the issue is that To fix this without breaking the other builds that share I've just pushed the fix, let's see if the CI turns green! |
777a546 to
a0dbfc8
Compare
|
Hi @richyreachy, the RISC-V CI failed due to a timeout. Would it be possible to split the build and test phases to prevent this? |
There's hard timeout limit(6 hours ) for CI jobs. Since test stage depends on the outcome of build, it may need some effects to figure out how to shrink the process. |
|
Hi @richyreachy, |
…itelist Currently, `cpu_features.cc` assumes any non-ARM architecture is x86/x64, which leads to a fatal missing `<cpuid.h>` error on architectures like RISC-V. This commit refactors the preprocessor macros to explicitly whitelist x86 architectures (`__x86_64__`, `__i386__`, `_M_X64`, `_M_IX86`). All other architectures (RISC-V, ARM, etc.) will now safely fall back to the default zero-initialization, allowing cross-compilation to succeed. Signed-off-by: ihb2032 <hebome@foxmail.com>
Introduce the RISC-V CI runner provided by the RISE project. This enables automated testing and building for the RISC-V architecture. Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
500df99 to
057035c
Compare
|
Hi @richyreachy,
|
The python test is still failing. @iaojnh please take a look at the streamer test failure. Looks like precision problem caused by randomly generated data. |
30dbacb to
6cb3676
Compare
b2391d6 to
51200f9
Compare
|
@richyreachy Could you please re-run the failed Python and C++ test jobs? They failed due to a transient runner environment issue, not a code error. Thanks! |
Done. please keep tabs on them. |
c7fa822 to
bcb76e3
Compare
bcb76e3 to
2d4ea48
Compare
34ed129 to
2979969
Compare
2979969 to
946a290
Compare
|
@richyreachy Good news is that all the other RISC-V tests have passed. As I pointed out earlier, the C++ test failure is just down to the hnsw_streamer_test case. Glad to hear it! Could @iaojnh please take a look at the streamer test failure? To my knowledge, it should already be resolved. Here's the fix: #375 |
|
@richyreachy Looks like the remaining C++ test failure is still stemming from hnsw_streamer_test. |
|
@richyreachy @iaojnh It looks like the CI is still failing on hnsw_streamer_test. Could you take another look? |
Currently, cpu_features.cc assumes that any architecture that is not __ARM_ARCH must be an x86/x64 architecture and attempts to include <cpuid.h>. This causes fatal compilation errors on other architectures like RISC-V.
Changes Proposed
This PR refactors the preprocessor directives to use an explicit "whitelist" approach:
Motivation
This resolves build failures on RISC-V environments and sets up a clean, safe foundation for potentially adding architecture-specific optimizations in the future.
closed #244