library/axi_hsci: Add HSCI IP core

library/axi_hsci/Makefile

@@ -0,0 +1,28 @@
+####################################################################################
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := axi_hsci
+
+GENERIC_DEPS += ../common/ad_rst.v
+GENERIC_DEPS += axi4_lite.sv
+GENERIC_DEPS += axi_hsci.sv
+GENERIC_DEPS += hsci_master_axi_slave.sv
+GENERIC_DEPS += hsci_master_logic.sv
+GENERIC_DEPS += hsci_master_regs_defs.vh
+GENERIC_DEPS += hsci_master_regs_regs.sv
+GENERIC_DEPS += hsci_master_top.sv
+GENERIC_DEPS += hsci_mcore.v
+GENERIC_DEPS += hsci_mdec.sv
+GENERIC_DEPS += hsci_menc.sv
+GENERIC_DEPS += hsci_mfrm_det.v
+GENERIC_DEPS += hsci_mlink_ctrl.sv
+GENERIC_DEPS += lfsr15_8.v
+GENERIC_DEPS += pulse_sync.v
+
+XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
+XILINX_DEPS += axi_hsci_ip.tcl
+
+include ../scripts/library.mk

library/axi_hsci/axi4_lite.sv

@@ -0,0 +1,83 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ns
+interface axi4_lite #(
+   DATA_WIDTH = 32,
+   ADDR_WIDTH = 32
+);
+
+  localparam WSTRB_WIDTH = DATA_WIDTH/8;
+
+  // Write address channel
+  logic                   awvalid;
+  logic                   awready;
+  logic [2:0]             awprot;
+  logic [ADDR_WIDTH-1:0]  awaddr;
+
+  // Write data channel
+  logic                   wvalid;
+  logic                   wready;
+  logic [WSTRB_WIDTH-1:0] wstrb;
+  logic [DATA_WIDTH-1:0]  wdata;
+
+  // Write response channel
+  logic                   bvalid;
+  logic                   bready;
+  logic [1:0]             bresp;
+
+  // Read address channel
+  logic                   arvalid;
+  logic                   arready;
+  logic [2:0]             arprot;
+  logic [ADDR_WIDTH-1:0]  araddr;
+
+  // Read response channel
+  logic                   rvalid;
+  logic                   rready;
+  logic [1:0]             rresp;
+  logic [DATA_WIDTH-1:0]  rdata;
+
+  modport master (
+    output awvalid, awprot, awaddr, wvalid, wstrb, wdata, bready, arvalid, arprot, araddr, rready,
+    input awready, wready, bvalid, bresp, arready, rvalid, rresp, rdata
+  );
+
+  modport slave (
+    output awready, wready, bvalid, bresp, arready, rvalid, rresp, rdata,
+    input awvalid, awprot, awaddr, wvalid, wstrb, wdata, bready, arvalid, arprot, araddr, rready
+  );
+
+endinterface

library/axi_hsci/axi_hsci.sv

@@ -0,0 +1,128 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ps/1ps
+import hsci_master_regs_pkg::*;
+
+module axi_hsci #(
+   parameter AXI_ADDR_WIDTH    =    15,
+   parameter AXI_DATA_WIDTH    =    32,
+   parameter REGMAP_ADDR_WIDTH =    16,
+   parameter S_AXI_ADDR_WIDTH  =    18
+) (
+  input  wire                                s_axi_aclk,
+  input  wire                                s_axi_aresetn,
+
+  input   wire [S_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,
+  input   wire [2:0]                         s_axi_awprot,
+  input   wire                               s_axi_awvalid,
+  input   wire                               s_axi_bready,
+  input   wire [AXI_DATA_WIDTH-1:0]          s_axi_wdata,
+  input   wire                               s_axi_wvalid,
+  input   wire                               s_axi_rready,
+  input   wire [(AXI_DATA_WIDTH/8)-1 : 0]    s_axi_wstrb,
+  input   wire [S_AXI_ADDR_WIDTH-1:0]        s_axi_araddr,
+  input   wire [2:0]                         s_axi_arprot,
+  input   wire                               s_axi_arvalid,
+
+  output  wire                               s_axi_wready,
+  output  wire                               s_axi_arready,
+  output  wire [1:0]                         s_axi_rresp,
+  output  wire [AXI_DATA_WIDTH-1:0]          s_axi_rdata,
+  output  wire                               s_axi_rvalid,
+  output  wire                               s_axi_awready,
+  output  wire [1:0]                         s_axi_bresp,
+  output  wire                               s_axi_bvalid,
+
+  input   wire                               hsci_pclk,
+  output       [7:0]                         hsci_menc_clk,
+  output       [7:0]                         hsci_mosi_data,
+  input   wire [7:0]                         hsci_miso_data,
+
+  output  wire                               hsci_pll_reset,
+  input   wire                               hsci_rst_seq_done,
+  input   wire                               hsci_pll_locked,
+  input   wire                               hsci_vtc_rdy_bsc_tx,
+  input   wire                               hsci_dly_rdy_bsc_tx,
+  input   wire                               hsci_vtc_rdy_bsc_rx,
+  input   wire                               hsci_dly_rdy_bsc_rx
+
+);
+
+  axi4_lite #(32,18)   axi();
+
+  assign axi.awaddr    =  s_axi_awaddr;
+  assign axi.awprot    =  s_axi_awprot;
+  assign axi.awvalid   =  s_axi_awvalid;
+  assign axi.bready    =  s_axi_bready;
+  assign axi.wdata     =  s_axi_wdata;
+  assign axi.wvalid    =  s_axi_wvalid;
+  assign axi.rready    =  s_axi_rready;
+  assign axi.wstrb     =  s_axi_wstrb;
+  assign axi.araddr    =  s_axi_araddr;
+  assign axi.arprot    =  s_axi_arprot;
+  assign axi.arvalid   =  s_axi_arvalid;
+
+  assign s_axi_wready   =  axi.wready;
+  assign s_axi_arready  =  axi.arready;
+  assign s_axi_rresp    =  axi.rresp;
+  assign s_axi_rdata    =  axi.rdata;
+  assign s_axi_rvalid   =  axi.rvalid ;
+  assign s_axi_awready  =  axi.awready;
+  assign s_axi_bresp    =  axi.bresp;
+  assign s_axi_bvalid   =  axi.bvalid;
+
+  hsci_master_top #(
+    .AXI_ADDR_WIDTH      (AXI_ADDR_WIDTH),
+    .AXI_DATA_WIDTH      (AXI_DATA_WIDTH),
+    .REGMAP_ADDR_WIDTH   (REGMAP_ADDR_WIDTH),
+    .S_AXI_ADDR_WIDTH    (S_AXI_ADDR_WIDTH)
+  ) hsci_master_top (
+    .axi_clk             (s_axi_aclk),
+    .axi_resetn          (s_axi_aresetn),
+    .axi                 (axi),
+    .hsci_pclk           (hsci_pclk),
+    .hsci_menc_clk       (hsci_menc_clk),
+    .hsci_mosi_data      (hsci_mosi_data),
+    .hsci_miso_data      (hsci_miso_data),
+    .hsci_pll_reset      (hsci_pll_reset),
+    .hsci_rst_seq_done   (hsci_rst_seq_done),
+    .hsci_pll_locked     (hsci_pll_locked),
+    .hsci_vtc_rdy_bsc_tx (hsci_vtc_rdy_bsc_tx),
+    .hsci_dly_rdy_bsc_tx (hsci_dly_rdy_bsc_tx),
+    .hsci_vtc_rdy_bsc_rx (hsci_vtc_rdy_bsc_rx),
+    .hsci_dly_rdy_bsc_rx (hsci_dly_rdy_bsc_rx));
+
+endmodule

library/axi_hsci/axi_hsci_constr.ttcl

@@ -0,0 +1,20 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+
+set_false_path \
+  -from [get_cells -hierarchical * -filter {NAME=~*hsci_master_top/hsci_master_logic/hsci_master_regs_regs/O_reg[hsci_bram_start_address][data][*]/C}] \
+  -to [get_cells -hierarchical * -filter {NAME=~*hsci_master_top/hsci_mcore/enc0/enc_addr_reg[*]/D}]
+
+set_false_path \
+  -from [get_cells -hierarchical * -filter {NAME=~*hsci_master_top/hsci_master_logic/hsci_master_regs_regs/O_reg[hsci_xfer_num][data][*]/C}] \
+  -to [get_cells -hierarchical * -filter {NAME=~*hsci_master_top/hsci_mcore/enc0/m_xfer_num_reg[*]/D}]
+
+set_false_path -from [get_cells -filter IS_SEQUENTIAL -hierarchical -regexp ".*O_reg.*"] -to [get_clocks -of_objects [get_ports {hsci_pclk}]]

library/axi_hsci/axi_hsci_ip.tcl

@@ -0,0 +1,57 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# ip
+
+source ../../scripts/adi_env.tcl
+source ../scripts/adi_ip_xilinx.tcl
+
+adi_ip_create axi_hsci
+adi_ip_files axi_hsci [list \
+  "../common/ad_rst.v" \
+  "../xilinx/common/ad_rst_constr.xdc" \
+  "axi_hsci.sv" \
+  "hsci_master_axi_slave.sv" \
+  "hsci_master_logic.sv" \
+  "hsci_master_regs_defs.vh" \
+  "hsci_master_regs_regs.sv" \
+  "hsci_master_top.sv" \
+  "hsci_mcore.v" \
+  "hsci_mdec.sv" \
+  "hsci_menc.sv" \
+  "hsci_mfrm_det.v" \
+  "hsci_mlink_ctrl.sv" \
+  "lfsr15_8.v" \
+  "pulse_sync.v" \
+  "axi4_lite.sv" ]
+
+adi_ip_properties axi_hsci
+adi_ip_ttcl axi_hsci "axi_hsci_constr.ttcl"
+set_property display_name "ADI AXI HSCI" [ipx::current_core]
+set_property description "ADI AXI HSCI" [ipx::current_core]
+# set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_hsci} [ipx::current_core]
+
+adi_init_bd_tcl
+
+proc add_reset {name polarity} {
+  set reset_intf [ipx::infer_bus_interface $name xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
+  set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
+  set_property value $polarity $reset_polarity
+}
+
+ipx::infer_bus_interface hsci_pclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+# ipx::infer_bus_interface hsci_data_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
+add_reset s_axi_aresetn ACTIVE_LOW
+
+ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]
+set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
+
+adi_add_auto_fpga_spec_params
+ipx::create_xgui_files [ipx::current_core]
+
+ipx::save_core [ipx::current_core]