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Lane rate computation must use the JESD204 parameter N'(NP). Fixes: 7d4673d ("iio: adc: ad9208: Initial HS ADC AD9208 family support") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Only set vco_cfg when its initialized. Fixes: 06897d6 ("iio: adc: ad9208: Enable ad9680 support in the ad9208 device driver") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Add AD9528 to the topology since it declares itself as jesd204-device; Since we have two separate typologies and only one clock chip. Make sure we include it in the topology which gets initialized first. Otherwise the CLK_SYNC state will reset the clocks and thus causing a link drop. This requires that the clock chip defaults match the other unhanded link. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
nunojsa
approved these changes
Nov 22, 2023
| jesd204-top-device = <0>; /* This is the TOP device */ | ||
| jesd204-link-ids = <0>; | ||
| jesd204-inputs = <&axi_ad9680_core 0 0>; | ||
| //jesd204-ignore-errors; |
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nit: I would remove the line as it's a comment
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It's a useful comment for support purposes. If someone runs into this problem again. It's easier to just point to that line and instruct uncomment...
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