v0.3.0

What's Changed

• feat: pin c4o-core 2.20 and document the new results page by @anlit75 in #63
• feat: pin c4o-core 2.21 and measure code coverage by @anlit75 in #64
• feat: rename to rtl/ and tb/, pin c4o-core 2.22, add a regression list by @anlit75 in #65
• docs: apply STE writing rules to the public English text by @anlit75 in #66
• fix: keep the weak delay cells out of blinky's reset buffering by @anlit75 in #67
• fix: keep all the weak buffers out of the physical flow by @anlit75 in #68

Full Changelog: v0.2.0...v0.3.0

v0.2.0

What's Changed

• feat: ship cocotb tests only and run them on the gates too by @anlit75 in #62

Full Changelog: v0.1.0...v0.2.0

v0.1.0

What's Changed

• refactor: migrate to c4o-core v1.1.1 and simplify build system by @anlit75 in #1
• ci: optimize pipeline with pdk caching and comprehensive artifacts by @anlit75 in #2
• fix: optimize makefile for devcontainers and guard gds flow by @anlit75 in #3
• fix: compile testbench in make sim by @anlit75 in #4
• chore: ignore runs/, and publish the GDS as a release on v* tags by @anlit75 in #5
• build: bump c4o-core 1.2.0 -> 1.3.0 by @anlit75 in #6
• feat!: migrate to LibreLane and a YAML config by @anlit75 in #7
• test: make tb_blinky actually verify blinky by @anlit75 in #8
• fix: run the devcontainer as a non-root user by @anlit75 in #9
• docs: document the Dev Container the repo ships by @anlit75 in #10
• build: bump c4o-core to 2.1.0 by @anlit75 in #11
• feat: show what the flow measured when gds finishes by @anlit75 in #12
• docs: add a pull request template; always run CI on pull requests by @anlit75 in #13
• fix: run the devcontainer as root again by @anlit75 in #14
• feat: simulate the gates, not just the RTL by @anlit75 in #15
• feat: add a cocotb example by @anlit75 in #16
• fix: make gds work inside the Dev Container by @anlit75 in #17
• feat: lead with what LibreLane does not do, and stop hardcoding blinky by @anlit75 in #18
• feat: let the flow resume, and drop an extension that no longer exists by @anlit75 in #19
• feat: draw the circuit, and catch a wrong DESIGN_NAME in 0.2s not 3 minutes by @anlit75 in #20
• fix: stop CI demanding two kinds of test nobody opted into by @anlit75 in #21
• docs: show people how to write the test, not just that they should by @anlit75 in #22
• feat: let the die size itself around the design by @anlit75 in #23
• docs: a README you can finish before the first run does by @anlit75 in #24
• test: check every cycle against a model, not three moments by hand by @anlit75 in #25
• ci: catch a c4o-core tag bumped in one place and missed in another by @anlit75 in #26
• ci: pin c4o-core to the minor, and take 2.8 with it by @anlit75 in #27
• docs: stop quoting numbers that go out of date by @anlit75 in #28
• docs: say what a reader has to know, not just what to install by @anlit75 in #29
• docs: fix the command that printed nothing, and the advice that told you to leave by @anlit75 in #30
• docs: say what the summary leaves out, and what gatesim does not check by @anlit75 in #31
• docs: stop offering a shortcut that measures the wrong gates by @anlit75 in #32
• docs: point a reader at the repository that answers their question by @anlit75 in #33
• docs: say what Ciel is where its name first appears by @anlit75 in #34
• docs: say that your own SDC file works, because it does by @anlit75 in #35
• feat: let one PDK serve several checkouts, via PDK_ROOT by @anlit75 in #36
• docs: list make all in make help, and untangle one sentence by @anlit75 in #37
• docs: correct what reports reset timing, and say the image is amd64 only by @anlit75 in #38
• ci: hold the arm64 claim to the registry, and look at reset timing by @anlit75 in #39
• docs: undo a contradiction I left behind, and say synth has no area by @anlit75 in #40
• docs: SystemVerilog works here now, and CI holds the claim by @anlit75 in #41
• feat: publish the results page to GitHub Pages from main by @anlit75 in #42
• feat: the results page shows signoff, timing, area and power by @anlit75 in #43
• feat: the results page draws a waveform, and report names its power corner by @anlit75 in #44
• docs: make the commercial tool mapping a table, and finish it by @anlit75 in #45
• feat: CI run summary shows cocotb verdicts and signoff; bump c4o-core to 2.12 by @anlit75 in #46
• feat: README becomes a front page, and c4o-core 2.13 redesigns the results page by @anlit75 in #47
• docs: the front page shows a test catching a bug, and opens a Codespace in one click by @anlit75 in #48
• docs: the pin comment says fixes reach 2.13 only while it is the newest minor by @anlit75 in #49
• fix: the published results page names the commit it was built from by @anlit75 in #50
• feat: move to c4o-core 2.14, whose results page reads as a portfolio piece by @anlit75 in #51
• docs: what trips up a first design of your own by @anlit75 in #52
• feat: move to c4o-core 2.15, whose diagrams download and whose power bars read as shares by @anlit75 in #53
• docs: write the README and guide in short, single-idea sentences by @anlit75 in #54
• fix: the documented make gds resume works, and a full re-run leaves one run by @anlit75 in #55
• docs: say which config keys are optional, which take globs, and that make sim runs one top by @anlit75 in #56
• docs: README tagline matches the repo description, and says the flow stops at the GDS by @anlit75 in #57
• ci: use the PDK cache, skip the flow for docs-only pull requests, pull LibreLane early by @anlit75 in #58
• ci: call the shared c4o-core actions, and keep the template's own checks to the template by @anlit75 in #60
• feat: the Makefile takes its commands from the c4o-core image, and moves to 2.17 by @anlit75 in #61

New Contributors

• @anlit75 made their first contribution in #1

Full Changelog: https://github.com/anlit75/ChipForAll/commits/v0.1.0