v3.10.0 — JOSS Paper, MNIST-on-FPGA Demo, Documentation Overhaul

Highlights

JOSS Paper (submission-ready)

• paper/paper.md + paper.bib — 12 references with DOIs
• MNIST demo results, Brian2 comparison, formal verification data

MNIST-on-FPGA Demo

• examples/mnist_fpga/demo.py — end-to-end: train → Q8.8 quantise → SC simulate → Verilog export
• Float 94.2%, Q8.8 94.2%, SC 94.0% (L=1024, sign-magnitude encoding)
• hdl/sc_dense_matrix_layer.v — per-neuron weight dense layer for classification
• Resource estimate: 16→10 = ~56K LUTs (fits Artix-7 100T)

Vivado Tooling

• tools/vivado_impl.tcl — non-project synthesis/implementation flow
• tools/vivado_report.py — parse timing, utilisation, power reports to JSON

Tutorial

• docs/tutorials/fpga_in_20_minutes.md — 6-section deployment guide

Documentation Overhaul

• README benchmarks section: Rust SIMD, Brian2 comparison, Yosys synthesis
• All 10 HDL modules listed with descriptions
• Zenodo DOI updated to 10.5281/zenodo.18906614
• Test counts, Python version, coverage data corrected across all docs

Fixes

• Zenodo author list corrected (sole author: Miroslav Šotek)
• DOI badge points to latest Zenodo record

Metrics

• 1 100+ Python tests, 108 Rust tests
• 98% coverage (enforced gate)
• 10 synthesisable Verilog modules
• 11 CI workflows, all SHA-pinned