fix: replace RISC-V cpu_relax fence.i with pause hint for spin-wait#3374
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fix: replace RISC-V cpu_relax fence.i with pause hint for spin-wait#3374Felix-Gong wants to merge 1 commit into
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fence.i is an instruction-synchronization barrier that flushes the icache, too heavy for a spin-wait hint. Use the pause hint (Zihintpause extension, encoding 0x0100000F) instead, matching the RISC-V Linux kernel's ALT_RISCV_PAUSE() behavior. .word is used to emit the raw encoding for maximum assembler compatibility, avoiding dependency on either the 'pause' mnemonic (requires Zihintpause in -march) or the .insn directive (requires recent binutils/Clang). Signed-off-by: Xiaofei Gong <gongxiaofei24@iscas.ac.cn> Signed-off-by: YuanSheng <yuansheng@isrc.iscas.ac.cn>
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Description
fence.iis an instruction-synchronization barrier on RISC-V that flushes the instruction cache. Using it incpu_relax()for spin-wait loops is unnecessarily heavy — it should only be used after writing code (e.g., JIT compilation, self-modifying code).Fix
Replace
fence.iwith the pause hint (Zihintpause extension, encoding0x0100000F). The encodingfence 0, 1is a HINT on all RISC-V implementations: it never traps and is ignored on CPUs without Zihintpause. On CPUs with Zihintpause it provides a multi-cycle stall hint that reduces power and improves resource fairness during spin loops. Matches the RISC-V Linux kernel'sALT_RISCV_PAUSE()behavior..word 0x0100000fis used instead of thepausemnemonic for maximum assembler compatibility, avoiding dependency on thepausemnemonic (requireszihintpausein-march) or the.insndirective (requires recent binutils/Clang).Verification
.word 0x0100000fon RISC-V 64-bit server (SG2044, rv64gcv) with GCC 12.3.1 and Clang (both tested with-march=rv64gc,rv64gcv, andrv64gcv_zihintpause)pauseencoding0x0100000femitted in all casesriscv64-linux-gnu-g++(GCC 13) also confirmed correct encodingReferences