imxrt - interrupt serial storm, add DTCM and set up I and D cache #175
Merged
patacongo merged 11 commits intoapache:pr175from Jan 29, 2020
Merged
imxrt - interrupt serial storm, add DTCM and set up I and D cache #175patacongo merged 11 commits intoapache:pr175from
patacongo merged 11 commits intoapache:pr175from
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The target would randomly hang in the serial isr.
The priv->ie and the hardware were inconsistent.
The isr used the priv->ie to gate offloading
the RX data. Bang! Hung.
imxrt_disableuartint(priv, &ie);
ret = imxrt_setup(dev);
/* Restore the interrupt state */
imxrt_restoreuartint(priv, ie);
interrupt-> Of no return
priv->ie = ie;
On a fast cpu with FIFO, this will not work
with out proper protections.
Preserve the existing API and enabed better granualriy on setting.
Contributor
|
It is late here. I will review / merge in the morning. |
Contributor
Author
|
Enjoy your evening!
Thank you!
|
Contributor
|
+1 |
Ouss4
reviewed
Jan 29, 2020
Co-Authored-By: Abdelatif Guettouche <abdelatif.guettouche@gmail.com>
Ouss4
approved these changes
Jan 29, 2020
patacongo
pushed a commit
that referenced
this pull request
Jan 29, 2020
* Serial Fixed interrupt storm
The target would randomly hang in the serial isr.
The priv->ie and the hardware were inconsistent.
The isr used the priv->ie to gate offloading
the RX data. Bang! Hung.
imxrt_disableuartint(priv, &ie);
ret = imxrt_setup(dev);
/* Restore the interrupt state */
imxrt_restoreuartint(priv, ie);
interrupt-> Of no return
priv->ie = ie;
On a fast cpu with FIFO, this will not work
with out proper protections.
* Serial: Conditionally enable 9 bit mode
* armv7-mi/mpu.hi: Restructure API
Preserve the existing API and enabled better granualriy on
setting.
* Enable MPU for non protected builds to set cache
* mpuinit use symbolic values for addresses
* Allow DTCM on HEAP
* allocateheap Fix Coding style
chengguizi
pushed a commit
to nusrobomaster/nuttx
that referenced
this pull request
Jan 2, 2021
…D cache (apache#175) * Serial Fixed interrupt storm The target would randomly hang in the serial isr. The priv->ie and the hardware were inconsistent. The isr used the priv->ie to gate offloading the RX data. Bang! Hung. imxrt_disableuartint(priv, &ie); ret = imxrt_setup(dev); /* Restore the interrupt state */ imxrt_restoreuartint(priv, ie); interrupt-> Of no return priv->ie = ie; On a fast cpu with FIFO, this will not work with out proper protections. * Serial: Conditionally enable 9 bit mode * armv7-mi/mpu.hi: Restructure API Preserve the existing API and enabled better granualriy on setting. * Enable MPU for non protected builds to set cache * mpuinit use symbolic values for addresses * Allow DTCM on HEAP * allocateheap Fix Coding style
Shunichi-K
pushed a commit
to SPRESENSE/nuttx
that referenced
this pull request
Nov 7, 2022
Add critical section to scu one-shot sequencer
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Found out the imx does not configure the cache for the memory map
ran nxstyle ignored the errors for imxrt_mpuinit.c and mpu.h that look like the tool is confused.
Built 1020, 1050, 1060 evk - passed