riscv/common/espressif: Fix spi slave driver

Documentation/applications/examples/spislv_test/index.rst

@@ -3,7 +3,12 @@
 
 A simple example for the device functioning as an SPI slave. 
 This example can be used to validate communication with another device 
-operating as an SPI master. If the spitool is used on the other device,
+operating as an SPI master. 
+This example contains a hardcoded buffer, which is: 
+{0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
+0x0C, 0x0D, 0x0E, 0x0F}. Whenever data is received,
+this example will send the same number of bytes received,
+consuming the hardcoded buffer in a circular manner.
 and the following command is sent:
 
 ``spi exch -x 4 deadbeef``
@@ -12,9 +17,7 @@ The expected response in device running spislv_test app is:
 
 .. code-block:: bash
 
-  Slave: 4 Bytes reads
-  Value in hex form from /dev/spislv2: de ad be ef
-  Slave: Writing value back to /dev/spislv2
+  Queued for sending to master: 01 02 03 04
 
 
 This test requires the device to be configured in SPI slave mode.(your

arch/risc-v/src/common/espressif/esp_spi_slave.c

@@ -541,6 +541,31 @@ static void spislave_setup_tx_dma(struct spislave_priv_s *priv)
 }
 #endif
 
+/****************************************************************************
+ * Name: spi_slave_prepare_data
+ *
+ * Description:
+ *   Prepare the SPI Slave controller for transmitting data in CPU-controlled
+ *   mode. This function resets the SPI Slave hardware, writes the data to
+ *   the TX buffer, and resets the TX FIFO.
+ *
+ * Input Parameters:
+ *   priv           - Private SPI Slave controller structure
+ *   nbits_to_send  - Number of bits to send in the next transaction
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+static inline void spi_slave_prepare_data(struct spislave_priv_s *priv,
+                      ssize_t nbits_to_send)
+{
+  spi_ll_slave_reset(priv->ctx.hw);
+  spi_ll_write_buffer(priv->ctx.hw, priv->tx_buffer, nbits_to_send);
+  spislave_cpu_tx_fifo_reset(priv->ctx.hw);
+}
+
 /****************************************************************************
  * Name: spislave_prepare_next_tx
  *
@@ -558,12 +583,15 @@ static void spislave_setup_tx_dma(struct spislave_priv_s *priv)
 
 static void spislave_prepare_next_tx(struct spislave_priv_s *priv)
 {
+  uint32_t nbits_to_send;
+
   if (priv->tx_length != 0)
     {
 #ifdef CONFIG_ESPRESSIF_SPI2_DMA
       spislave_setup_tx_dma(priv);
 #else
-      spi_slave_hal_prepare_data(&priv->ctx);
+      nbits_to_send = priv->nbits * priv->tx_length;
+      spi_slave_prepare_data(priv, nbits_to_send);
 #endif
       priv->is_tx_enabled = true;
     }
@@ -572,11 +600,15 @@ static void spislave_prepare_next_tx(struct spislave_priv_s *priv)
       spiwarn("TX buffer empty! Disabling TX for next transaction\n");
 
 #ifndef CONFIG_ESPRESSIF_SPI2_DMA
-      spislave_cpu_tx_fifo_reset(priv->ctx.hw);
+      memset(priv->tx_buffer, 0, sizeof(priv->tx_buffer));
+      spi_slave_prepare_data(priv, priv->ctx.rcv_bitlen);
 #endif
 
       priv->is_tx_enabled = false;
     }
+
+    spi_ll_slave_set_rx_bitlen(priv->ctx.hw, priv->ctx.rcv_bitlen);
+    spi_ll_slave_set_tx_bitlen(priv->ctx.hw, priv->ctx.rcv_bitlen);
 }
 
 /****************************************************************************

boards/risc-v/esp32c6/esp32c6-devkitc/configs/spislv/defconfig

@@ -0,0 +1,58 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_SPI_EXCHANGE is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c6-devkitc"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y
+CONFIG_ARCH_CHIP="esp32c6"
+CONFIG_ARCH_CHIP_ESP32C6=y
+CONFIG_ARCH_CHIP_ESP32C6WROOM1=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEV_ZERO=y
+CONFIG_ESPRESSIF_ESP32C6=y
+CONFIG_ESPRESSIF_SPI2=y
+CONFIG_ESPRESSIF_SPI2_CSPIN=15
+CONFIG_ESPRESSIF_SPI2_SLAVE=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXAMPLES_SPISLV=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_BACKTRACE=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_SLAVE_DRIVER=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_DUMPSTACK=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_OSTEST=y
+CONFIG_UART0_SERIAL_CONSOLE=y

boards/risc-v/esp32c6/esp32c6-devkitm/configs/spislv/defconfig

@@ -21,19 +21,15 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARDCTL_RESET=y
 CONFIG_BOARD_LOOPSPERMSEC=15000
 CONFIG_BUILTIN=y
-CONFIG_DEBUG_FEATURES=y
 CONFIG_DEBUG_FULLOPT=y
-CONFIG_DEBUG_SPI=y
-CONFIG_DEBUG_SPI_ERROR=y
-CONFIG_DEBUG_SPI_INFO=y
-CONFIG_DEBUG_SPI_WARN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_ZERO=y
 CONFIG_ESPRESSIF_ESP32C6=y
 CONFIG_ESPRESSIF_SPI2=y
 CONFIG_ESPRESSIF_SPI2_CSPIN=15
 CONFIG_ESPRESSIF_SPI2_SLAVE=y
 CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXAMPLES_SPISLV=y
 CONFIG_FS_PROCFS=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INIT_ENTRYPOINT="nsh_main"