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{bp-19229} arch/riscv: Add CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI for fence.i#19291

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xiaoxiang781216 merged 1 commit into
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Jul 3, 2026
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{bp-19229} arch/riscv: Add CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI for fence.i#19291
xiaoxiang781216 merged 1 commit into
apache:releases/13.0from
jerpelea:bp-19229

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@jerpelea

@jerpelea jerpelea commented Jul 3, 2026

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Summary

The fence.i instruction is only available when the Zifencei extension (CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI) is supported by the hardware.

This commit adds a macro wrapper around fence.i usages to prevent compilation errors on toolchains or targets where the Zifencei extension is absent.

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The fence.i instruction is only available when the Zifencei extension
(CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI) is supported by the hardware.

This commit adds a macro wrapper around fence.i usages to prevent
compilation errors on toolchains or targets where the Zifencei
extension is absent.

Signed-off-by: Chengdong Wang <wangcd91@gmail.com>
@github-actions github-actions Bot added Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: S The size of the change in this PR is small labels Jul 3, 2026
@jerpelea

jerpelea commented Jul 3, 2026

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@acassis ping

@xiaoxiang781216 xiaoxiang781216 merged commit fa534b7 into apache:releases/13.0 Jul 3, 2026
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@jerpelea jerpelea deleted the bp-19229 branch July 4, 2026 11:49
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Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: S The size of the change in this PR is small

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4 participants