{bp-19415} drivers/spi/ice40: fix operator precedence in final clock cycle count - #19613
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ice40_endwrite() computes how many dummy SPI bytes to clock out after
the bitstream to finish FPGA configuration with:
for (size_t i = 0; i < ICE40_SPI_FINAL_CLK_CYCLES + 7 / 8; i++)
`/` binds tighter than `+` in C, so this parses as
ICE40_SPI_FINAL_CLK_CYCLES + (7 / 8) = 160 + 0 = 160, i.e. the "+ 7 / 8"
is a silent no-op. The macro name and the classic `(n + 7) / 8`
ceiling-division idiom (used elsewhere in embedded code to convert a
bit/cycle count into a byte count) make clear the intent was to send
ceil(ICE40_SPI_FINAL_CLK_CYCLES / 8) = 20 bytes (160 SPI clock cycles,
matching the macro name). Instead the unmodified code sends 160 bytes,
i.e. 1280 clock cycles - 8x more than intended.
Fix by parenthesizing the ceiling-division: (ICE40_SPI_FINAL_CLK_CYCLES
+ 7) / 8, which evaluates to 20, restoring the intended 160-clock-cycle
finalization sequence.
Fixes apache#19367
Assisted-by: Claude Code:claude-sonnet-5
Signed-off-by: yi chen <94xhn1@gmail.com>
jerpelea
requested review from
acassis,
cederom,
linguini1,
lupyuen and
xiaoxiang781216
August 3, 2026 07:48
xiaoxiang781216
approved these changes
Aug 3, 2026
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Summary
ice40_endwrite() computes how many dummy SPI bytes to clock out after the bitstream to finish FPGA configuration with:
/binds tighter than+in C, so this parses as ICE40_SPI_FINAL_CLK_CYCLES + (7 / 8) = 160 + 0 = 160, i.e. the "+ 7 / 8" is a silent no-op. The macro name and the classic(n + 7) / 8ceiling-division idiom (used elsewhere in embedded code to convert a bit/cycle count into a byte count) make clear the intent was to send ceil(ICE40_SPI_FINAL_CLK_CYCLES / 8) = 20 bytes (160 SPI clock cycles, matching the macro name). Instead the unmodified code sends 160 bytes, i.e. 1280 clock cycles - 8x more than intended.Fix by parenthesizing the ceiling-division: (ICE40_SPI_FINAL_CLK_CYCLES
Fixes #19367
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