libc/atomic: refactor inline arch atomics, add atomic_ptr_t/atomic64/cmpxchg_release_acquire by zhangyu-duck · Pull Request #20043 · apache/nuttx

zhangyu-duck · 2026-09-02T07:56:26Z

Summary

Refactor NuttX's atomic operations to support inline arch-specific implementations, add new atomic types/variants, and provide 64-bit atomic support via spinlock.

Commits

include/atomic: add atomic_ptr_t type and operations — add pointer-width atomic type and operations
libc/atomic: support inline arch atomic for tricore — tricore inline atomic_*_4 via swap.w/cmpswap.w
libc/atomic: support inline arch atomic for generic IRQ path — generic IRQ/hwspinlock-based atomic path for archs without hardware atomics
libc/atomic: merge tricore arch_atomic.c into machine/arch_atomic.c — unify tricore atomic implementation into the generic machine/arch_atomic.c
include/atomic: add cmpxchg_release_acquire memory order variant — new cmpxchg memory order matching DPDK RTS ring tail-commit ordering
libc: realize atomic64 via a spinlock helper — 8-byte atomic symbols on a single spinlock for archs without native 64-bit support

Impact

New atomic_ptr_t type: pointer-width atomic type and operations (commit 1)
TriCore inline atomic: atomic_*_4 inlined via swap.w/cmpswap.w hardware instructions, no function call overhead (commit 2)
Generic IRQ/hwspinlock path: archs without hardware atomics get inline atomic via IRQ disable or hwspinlock (commit 3)
Unification: tricore-specific arch_atomic.c merged into generic machine/arch_atomic.c (commit 4)
New memory order: atomic_cmpxchg_release_acquire and atomic_try_cmpxchg_release_acquire for 32/64/pointer-width (commit 5)
64-bit atomics: all atomic_*_8, __atomic_*_8, sync_*_8, __sync_*_8 symbols provided via libs/libc/machine/arch_atomic64.c on a single spinlock (g_atomic64_lock), using spin_lock_irqsave for SMP correctness and local ISR safety; all helpers weak_function so archs with native 64-bit support can override at link time (commit 6)

Add atomic_ptr_t that maps to atomic_t on 32-bit platforms and atomic64_t on 64-bit platforms based on UINTPTR_MAX. All atomic_ptr_xx operations (set, read, add, sub, and, or, xor, xchg, cmpxchg, try_cmpxchg with memory order variants) are mapped to the corresponding atomic_xx or atomic64_xx macros accordingly. Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>

When CONFIG_LIBC_ATOMIC_ARCH is selected, atomic.h includes arch/atomic.h which provides static inline atomic_*_4 operations using arch-specific helpers. This eliminates function call overhead for NuttX atomic API. For Tricore, the inline functions use hardware helpers (tricore_atomic_swap, tricore_atomic_cmpswap) implemented with inline assembly (swap.w, cmpswap.w), avoiding the iLLD dependency. The arch_atomic.c retains __atomic_*_4 symbols with external linkage for GCC libatomic ABI compatibility. Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>

github-actions · 2026-09-02T08:22:41Z

MemBrowse Memory Report

arduino-mega2560

flash: .text -2,108 B (-3.2%, 62,984 B / 262,144 B, total: 24% used)

rx65n-rsk2mb

ROM: .text -1,344 B (-1.5%, 85,536 B / 2,097,152 B, total: 4% used)
No memory changes detected for:
esp32-devkitc
hifive1-revb
mirtoo
qemu-armv8a
qemu-intel64
s698pm-dkit
stm32-nucleo-f103rb

1. Add include/nuttx/lib/arch_atomic.h with inline atomic_*_4/8 and __sync_*_{1,2,4,8} operations using IRQ disable/enable or hwspinlock under CONFIG_LIBC_ATOMIC_IRQ / CONFIG_LIBC_ATOMIC_HWSPINLOCK. 2. Include the new header from include/nuttx/atomic.h so the NuttX atomic API becomes inline (no function call overhead). 3. Reduce libs/libc/machine/arch_atomic.c to only export __atomic_* and __sync_* symbols for GCC libatomic ABI; delete the local arch_atomic.h and arch_atomic64.c (superseded); update Make.defs and CMakeLists.txt accordingly. 4. Fix a pre-existing race in SYNC_*_FETCH macros where the return value was read from shared memory after releasing the lock; now captured in a local variable before unlocking. Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>

1. Add ARCH_HAVE_ATOMIC_4 guard in arch/tricore/include/atomic.h so the tricore arch declares which sizes have hardware atomic support. 2. Extend include/nuttx/lib/arch_atomic.h to #undef arch overrides and provide IRQ-based inline fallback for sizes the arch does not support, so generic code covers all {1,2,4,8} sizes uniformly. 3. Update libs/libc/machine/arch_atomic.c to gate per-size symbol export on ARCH_HAVE_ATOMIC_X and 64-bit on UINTPTR_MAX > UINT32_MAX; delete libs/libc/machine/tricore/arch_atomic.c (now merged into the generic machine/arch_atomic.c). 4. Drop tricore-specific arch_atomic.c references from libs/libc/machine/tricore/{Make.defs,CMakeLists.txt}. Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>

1. Add atomic_cmpxchg_release_acquire and atomic_try_cmpxchg_release_acquire for 32-bit (atomic_compare_exchange_4) using RELEASE on CAS success. 2. Add 64-bit counterparts atomic64_cmpxchg_release_acquire and atomic64_try_cmpxchg_release_acquire (atomic_compare_exchange_8). 3. Add pointer-width aliases atomic_ptr_cmpxchg_release_acquire and atomic_ptr_try_cmpxchg_release_acquire for both 64-bit and 32-bit pointer configurations, expanding the existing ptr_*_cmpxchg family. 4. Use ACQUIRE on CAS failure so the retry path re-acquires visibility of updates from other threads, matching the ordering used by DPDK RTS ring tail-commit CAS. Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>

libc/machine/arch_atomic64.c implementing atomic_*_8 on a single spinlock. All helpers are weak_function so an arch with native 64-bit support overrides at link time Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>

xiaoxiang781216 · 2026-09-04T15:32:07Z

  ARCH_ATOMIC_FETCH_OP(prefix ## _fetch_or_ ## n, t, n, |)               \
  ARCH_ATOMIC_FETCH_OP(prefix ## _fetch_xor_ ## n, t, n, ^)

+#define ARCH_HAVE_ATOMIC_4


why add here

xiaoxiang781216 · 2026-09-04T15:34:10Z

 #include <nuttx/config.h>

-#define ARCH_ATOMIC_SPECIFIER
+#define ARCH_ATOMIC_SPECIFIER weak_function


why need weak

xiaoxiang781216 · 2026-09-04T15:34:30Z

 #ifdef ARCH_HAVE_ATOMIC_4
 ARCH_ATOMIC_DEFINE(__atomic, uint32_t, 4)
 #endif
-#ifdef ARCH_HAVE_ATOMIC_8


xiaoxiang781216 · 2026-09-04T15:36:07Z

+ * but 64 bit atomics are rare enough that a single lock is not a bottleneck.
+ */
+
+static spinlock_t g_atomic64_lock = SP_UNLOCKED;


should use irq_save/restore in UP, could share with 32bit implementation

xiaoxiang781216 · 2026-09-04T15:36:23Z

+
+static inline irqstate_t atomic64_lock(void)
+{
+  return spin_lock_irqsave(&g_atomic64_lock);


let's inline the implementation too

xiaoxiang781216 · 2026-09-04T15:37:11Z

+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ATOMIC64_STORE(func, t)                                       \


let's reuse ATOMIC_DEFINE we can refine ATOMIC_DEFINE to accept the lock/unlock funciton

xiaoxiang781216 · 2026-09-04T15:38:53Z

 #define ARCH_HAVE_ATOMIC_1
 #define ARCH_HAVE_ATOMIC_2
 #define ARCH_HAVE_ATOMIC_4
-#define ARCH_HAVE_ATOMIC_8


let's keep, but provide the different lock/unlock for 64:

atomic for 64bit arch

irq save/restore for UP&32bit

spinlock for SMP&32bit

CV-Bowen added 2 commits August 31, 2026 20:51

github-actions Bot added Arch: tricore Issues related to the TriCore architecture from Infineon Area: OS Components OS Components issues Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. labels Sep 2, 2026

CV-Bowen and others added 4 commits September 3, 2026 15:30

libc: realize atomic64 via a spinlock helper

2802f3b

libc/machine/arch_atomic64.c implementing atomic_*_8 on a single spinlock. All helpers are weak_function so an arch with native 64-bit support overrides at link time Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>

zhangyu-duck force-pushed the atomic_part2 branch from 55f6842 to 2802f3b Compare September 3, 2026 08:08

zhangyu-duck marked this pull request as ready for review September 4, 2026 01:49

zhangyu-duck requested review from masayuki2009 and xiaoxiang781216 as code owners September 4, 2026 01:49

xiaoxiang781216 reviewed Sep 4, 2026

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libc/atomic: refactor inline arch atomics, add atomic_ptr_t/atomic64/cmpxchg_release_acquire - #20043

libc/atomic: refactor inline arch atomics, add atomic_ptr_t/atomic64/cmpxchg_release_acquire#20043
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