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arch/arm/stm32h7: poll MDIO completion in microseconds, not 5 ms steps #20067

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Merged
acassis merged 1 commit into from
Sep 7, 2026
+14 −9
Merged

arch/arm/stm32h7: poll MDIO completion in microseconds, not 5 ms steps #20067

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23 changes: 14 additions & 9 deletions arch/arm/src/stm32h7/stm32_mdio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ struct stm32_mdio_lowerhalf_s
{
struct mdio_lowerhalf_s base;

/* MDIO bus timeout in milliseconds */
/* MDIO bus timeout in microseconds */

int timeout;
};
Expand Down Expand Up @@ -95,7 +95,7 @@ struct stm32_mdio_lowerhalf_s g_stm32_mdio_lowerhalf =
{
.ops = &g_stm32_mdio_ops
},
.timeout = 10
.timeout = 10000
};

/****************************************************************************
Expand Down Expand Up @@ -131,9 +131,14 @@ static int stm32_c22_read(struct mdio_lowerhalf_s *dev, uint8_t phydev,

stm32_putreg(regval, STM32_ETH_MACMDIOAR);

/* Wait for the transfer to complete */
/* Wait for the transfer to complete. A Clause 22 frame is 64 MDC
* cycles, about 30 us at a 2.5 MHz MDC, so poll at a fraction of that.
* A millisecond delay here turns every PHY register access into a
* busy-wait far longer than the transfer, and the autonegotiation link
* wait in stm32_phyinit() issues thousands of them.
*/

for (to = priv->timeout; to >= 0; to--)
for (to = priv->timeout; to > 0; to -= 10)
{
if ((stm32_getreg(STM32_ETH_MACMDIOAR) & ETH_MACMDIOAR_MB) == 0)
{
Expand All @@ -142,10 +147,10 @@ static int stm32_c22_read(struct mdio_lowerhalf_s *dev, uint8_t phydev,
break;
}

up_mdelay(5);
up_udelay(10);
}

if (to <= 0)
if (retval < 0)
{
ninfo("MII transfer timed out: phydev: %04x regaddr: %04x\n",
phydev, regaddr);
Expand Down Expand Up @@ -192,18 +197,18 @@ static int stm32_c22_write(struct mdio_lowerhalf_s *dev, uint8_t phydev,

/* Wait for the transfer to complete */

for (to = priv->timeout; to >= 0; to--)
for (to = priv->timeout; to > 0; to -= 10)
{
if ((stm32_getreg(STM32_ETH_MACMDIOAR) & ETH_MACMDIOAR_MB) == 0)
{
retval = OK;
break;
}

up_mdelay(5);
up_udelay(10);
}

if (to <= 0)
if (retval < 0)
{
ninfo("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x"
"value: %04x\n", phydev, regaddr, value);
Expand Down
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