Bank Group and Activation Timings

Bank Group and Activation Timings: tFAW, tRRD_S, tRRD_L, tCCD_L

These three exist for two related but distinct reasons: peak current management and DDR4's bank-group architecture. Neither reason existed in earlier DDR generations in quite this form, which is why these timings get less attention in general RAM-tuning discussion than CL/tRCD/ tRP/tRAS.

Bank groups: what DDR4 added

Earlier DDR generations organized a chip as a flat set of banks (DDR3: typically 8). DDR4 groups those banks into bank groups — e.g. 4 groups of 4 banks each — because at DDR4's higher clock speeds, the shared internal data path from any bank to the I/O pins becomes a real bottleneck: two back-to-back column accesses within the same bank group have to share that data path and need more spacing than two accesses to different bank groups, which have independent-enough internal routing to overlap more aggressively. This is the reason almost every timing in this section comes in an "_S" (same bank group) and "_L" (different/"long", different bank group) pair — it's always the same-group case that's the looser (higher) number.

tFAW — Four Activate Window

A rolling window (typically ~15-30ns, module-dependent) inside which no more than four ACTIVATE commands may be issued, across any banks. This isn't a data-integrity constraint like tRAS — it's a peak current constraint. Every ACTIVATE draws a current spike as sense amplifiers across an entire row switch on simultaneously; four of those happening in too tight a window can exceed the chip's specified peak current draw (IDD limits), which is a real electrical/thermal concern, not just a protocol nicety. tFAW caps how "bursty" activation traffic can be, independent of which specific banks are involved.

tRRD_S / tRRD_L — Row-to-Row activate Delay

Minimum spacing between two ACTIVATE commands to different banks — the same-bank-group case (tRRD_S) is tighter timing pressure than the different-bank-group case (tRRD_L) precisely because same-group banks share more internal circuitry that needs time to settle between activations. In this project's reference kit, one module's SPD data shows tRRD_S as low as 2.5ns while its tRRD_L sits around 4.9ns — a concrete illustration of the same-group-is-tighter asymmetry.

tCCD_L (and tCCD_S)

Minimum spacing between two column commands (two back-to-back reads, or two back-to-back writes) — again, _L for same bank group (looser, because of the shared data-path bottleneck described above) and _S for different bank group. DDR4 SPD's base timing block only encodes tCCD_L directly; tCCD_S is fixed at a small constant value (typically 4 cycles) by the DDR4 standard itself rather than being module-specific, which is why spd-matchtable's "Suggested starting point" section labels tCCD_S=4 explicitly as an inferred constant rather than something read from SPD — see Command Rate and tCWL for the full list of values SPD simply doesn't carry.

Why these matter more as DIMM/rank count grows

All three of these timings become more consequential the more banks and ranks are actively being interleaved across — a single-rank, lightly loaded system barely notices tFAW/tRRD in practice, while a fully populated multi-rank mixed kit (like this project's own 2-dual-rank + 2-single-rank reference system) is exactly the scenario where getting these wrong shows up as real instability, because the memory controller is juggling far more simultaneous bank state.