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Merged
arghyabi merged 1 commit into from
Jul 19, 2026
Merged

Add new instruction WTSR and RDSR #97

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55 changes: 48 additions & 7 deletions Bootloader/Init.S
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Original file line number Diff line number Diff line change
@@ -1,18 +1,59 @@
; ================================================================
; 8-Bit Computer Bootloader
; ================================================================
; This routine executes immediately after a hardware reset.
;
; On entry to __app_main, the following conditions are guaranteed:
;
; -> SP = 0x7F
; -> A = 0
; -> B = 0
; -> C = 0
; -> D = 0
; -> ALU flags are initialized.
; -> 7-Segment display shows 0.
;
; ================================================================

__bl_start:
; Reset all the registers

; ------------------------------------------------------------
; Initialize the Stack Pointer.
; RAM address range : 0x00 - 0x7F
; Initial SP value : 0x7F
; The stack grows toward lower addresses.
; Each PUSH stores data at the current SP, then decrements SP.
; ------------------------------------------------------------
LDI A, 0x7F
WTSR SP

; ------------------------------------------------------------
; Clear all General Purpose Registers.
; ------------------------------------------------------------
LDI A, 0
LDI B, 0
LDI C, 0
LDI D, 0

; Reset the 7 segment display
; ------------------------------------------------------------
; Clear the 7-Segment Display.
; OUT displays the value of register A.
; ------------------------------------------------------------
OUT

; Reset all temp registers and flags
; ------------------------------------------------------------
; Initialize the ALU flags.
; A = 0 and B = 0, therefore:
;
; Zero = Set
; Equal = Set
; Carry = Cleared
; Greater = Cleared
; Less = Cleared
; ------------------------------------------------------------
ADD A, B

; Reset the stack pointer
LDSR SP, 0

; Jump to the main program
; ------------------------------------------------------------
; Transfer control to the user application.
; ------------------------------------------------------------
JMP __app_main
69 changes: 22 additions & 47 deletions Compiler/Assembler.py
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Original file line number Diff line number Diff line change
Expand Up @@ -103,10 +103,13 @@ def __init__(self, assemblyFile, outFile, silent, support8, padding, unsigned, n
'C': 0b10,
'D': 0b11
}
self.specialRegisterList= ['SP']
self.specialRegisterList= ['SP', 'MDR']
self.specialRegisterDict= {
'SP': 0b00
'SP' : 0b00,
'MDR': 0b01
}
self.allowedGpRegStr = ', '.join(self.registerList)
self.allowedSpRegStr = ', '.join(self.specialRegisterList)

# Load instruction opcodes and sizes from centralized config
configPath = os.path.join(os.path.dirname(__file__), '..', 'Microcode', 'MicroCodeConfig.yaml')
Expand Down Expand Up @@ -301,7 +304,7 @@ def errorPrint(index, error=None):

for payload in payloadList:
if payload not in self.registerList:
errorPrint(index, f"'{payload}' is not a register!!")
errorPrint(index, f"'{payload}' is not a register!! allowed registers are {self.allowedGpRegStr}")

if payloadList[0] == payloadList[1]: # Ignore the 'mov a a' or 'mov b b'; its NOP ..
pass
Expand All @@ -328,7 +331,7 @@ def errorPrint(index, error=None):

for payload in payloadList:
if payload not in self.registerList:
errorPrint(index, f"'{payload}' is not a register!!")
errorPrint(index, f"'{payload}' is not a register!! allowed registers are {self.allowedGpRegStr}")

payload = payloadList[0]
bitVal = bitVal | self.registerDict[payload]
Expand Down Expand Up @@ -401,7 +404,7 @@ def errorPrint(index, error=None):

destReg = payloadList[0]
if destReg not in self.registerList:
errorPrint(index, "Destination register not found!!")
errorPrint(index, f"Destination register not found!! allowed registers are {self.allowedGpRegStr}")

immediateVal = payloadList[1]
if isInt(immediateVal):
Expand Down Expand Up @@ -444,56 +447,28 @@ def errorPrint(index, error=None):
self.binArr.append(immediateVal)
self.addressIndex += 1

## Parse LDSR command | Format: SR01_0000
elif opcode == "LDSR":
if payloadLen != 2:
errorPrint(index, f"2 payload expected!!, but found {payloadLen}")

destReg = payloadList[0]
if destReg not in self.specialRegisterList:
errorPrint(index, "Destination register not found!!")

immediateVal = payloadList[1]
if isInt(immediateVal):
immediateVal = int(immediateVal)
elif isBinary(immediateVal):
immediateVal = int(immediateVal, 2)
elif isHex(immediateVal):
immediateVal = int(immediateVal, 16)
else:
errorPrint(index, f"{immediateVal} is not a valid value!!")
immediateVal = 0
## Parse WTSR, RDSR command | Format: SR01_0000, SR10_0000
elif opcode == "WTSR" or opcode == "RDSR":
if payloadLen != 1:
errorPrint(index, f"1 payload expected!!, but found {payloadLen}")

if self.unsigned:
if not (MIN_VAL_UNSIGNED_8_BIT <= immediateVal <= MAX_VAL_UNSIGNED_8_BIT):
errorPrint(index, "Value out of unsigned 8-bit range!")
if immediateVal < 0:
errorPrint(index, "Negative value not allowed in unsigned mode!")
else:
if immediateVal < 0: # if negative value then check if must be greater than or equal to -128
if immediateVal < MIN_VAL_SIGNED_8_BIT:
errorPrint(index, f"Value '{immediateVal}' out of signed 8-bit range!")
else:
immediateVal = get2sComplement(immediateVal)
else:
# if positive value then user might want as 2's complement value; but still is <= 255
if immediateVal > MAX_VAL_UNSIGNED_8_BIT:
errorPrint(index, f"Value '{immediateVal}' out of signed 8-bit range!")
for payload in payloadList:
if payload not in self.specialRegisterList:
errorPrint(index, f"'{payload}' is not a register!! allowed registers are {self.allowedSpRegStr}")

bitVal = bitVal | self.specialRegisterDict[destReg]
payload = payloadList[0]
bitVal = bitVal | self.specialRegisterDict[payload]

bitVal = bitVal << 6 # LDSR 6 bit
bitVal = bitVal << 6 # WTSR, RDSR are 6 bit
bitVal = bitVal | self.instructionDict[opcode]

if not self.silent:
self.printCompiledLine(line, bitVal, immediateVal)
self.printCompiledLine(line, bitVal)

self.binArr.append(bitVal)
self.addressIndex += 1

self.binArr.append(immediateVal)
self.addressIndex += 1


## Parse LDM, SAV command | Format: RRTT_0100
elif opcode == "LDM" or opcode == "SAV":
Expand All @@ -502,7 +477,7 @@ def errorPrint(index, error=None):

destReg = payloadList[0]
if destReg not in self.registerList:
errorPrint(index, "Destination register not found!!")
errorPrint(index, f"Destination register not found!! allowed registers are {self.allowedGpRegStr}")

memAddress = payloadList[1]
if isInt(memAddress):
Expand Down Expand Up @@ -540,7 +515,7 @@ def errorPrint(index, error=None):

reg = payloadList[0]
if reg not in self.registerList:
errorPrint(index, f"'{reg}' is not a register!!")
errorPrint(index, f"'{reg}' is not a register!! allowed registers are {self.allowedGpRegStr}")

bitVal = bitVal | self.registerDict[reg]
bitVal = bitVal << 6
Expand Down Expand Up @@ -666,7 +641,7 @@ def errorPrint(index, error=None):

for payload in payloadList:
if payload not in self.registerList:
errorPrint(index, f"'{payload}' is not a register!!")
errorPrint(index, f"'{payload}' is not a register!! allowed registers are {self.allowedGpRegStr}")

for payload in payloadList:
bitVal = bitVal << 2
Expand Down
10 changes: 5 additions & 5 deletions Config.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,14 @@ Project:

Version:
# Main version; any change requires a new version
MainVersion: "1.75.1.1088"
MainVersion: "1.76.0.1089"

Components:
Compiler : "1.22.0.1025"
Compiler : "1.23.0.1026"
Emulator : "1.6.0.1006"
Inspector : "1.1.0.1001"
Flasher : "1.8.1.1009"
7Segment : "1.4.0.1005"
ISA : "1.38.1.1045"
Document : "1.29.0.1037"
BootLoader: "1.0.0.1000"
ISA : "1.39.0.1046"
Document : "1.30.0.1038"
BootLoader: "1.1.0.1001"
45 changes: 35 additions & 10 deletions Docs/ISA.md
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Expand Up @@ -74,10 +74,19 @@ XOR B, C ; Logical XOR in B and C and keep in B
<td valign="top"><strong>SR01_0000</strong></td>
<td valign="top">SR01_0000</td>
<td valign="top">
<a href="#-instruction-nop">LDSR SR VV</a>
<a href="#-instruction-wtsr">WTSR SR</a>
</td>
<td valign="top">2 Byte</td>
<td valign="top">Load value immediately to Special Register</td>
<td valign="top">1 Byte</td>
<td valign="top">Write the value of register A to Special Register</td>
</tr>
<tr>
<td valign="top"><strong>SR10_0000</strong></td>
<td valign="top">SR10_0000</td>
<td valign="top">
<a href="#-instruction-rdsr">RDSR SR</a>
</td>
<td valign="top">1 Byte</td>
<td valign="top">Read the value of the Special Register into register A</td>
</tr>
<tr>
<td valign="top"><strong>SSDD_0001</strong></td>
Expand Down Expand Up @@ -253,17 +262,33 @@ This `NOP` instruction does nothing. It's kind of a blank instruction.

---------------

### ✅ Instruction: LDSR
This `LDSR` instruction load the value imediatly to the Spacial Register.
### ✅ Instruction: WTSR
This `WTSR` instruction write the value of regiister A to the Special Register.

#### `Ins. Format: LDSR SR VV`
#### `Ins. Format: WTSR SR`
#### `Bin. Format: SR01_0000`

| Instruction | Binary Value |
| :--- | :---: |
| LDSR SP 0xXX | 0001_0000 xxxx_xxxx |
| Instruction | Binary Value |
| :--- | :---: |
| WTSR SP | 0001_0000 |
| WTSR MD | 0101_0000 |

* 1001_0000, 1101_0000, are Reserved for future use

---------------

### ✅ Instruction: RDSR
This `RDSR` instruction read back the value of Special Register to the register A.

#### `Ins. Format: RDSR SR`
#### `Bin. Format: SR10_0000`

| Instruction | Binary Value |
| :--- | :---: |
| RDSR SP | 0010_0000 |
| RDSR SP | 0110_0000 |

* 0101_0000, 1001_0000, 1101_0000, are Reserved for future use
* 1010_0000, 1110_0000, are Reserved for future use

---------------

Expand Down
2 changes: 1 addition & 1 deletion Microcode/Instructions/InsADD.py
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Expand Up @@ -28,7 +28,7 @@
| O | T2IS0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| O | T2IS1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| O | FlgU | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| O | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| O | MdO | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| O | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
|---|-------|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| O | rAI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
Expand Down
2 changes: 1 addition & 1 deletion Microcode/Instructions/InsAND.py
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Expand Up @@ -28,7 +28,7 @@
| O | T2IS0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
| O | T2IS1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
| O | FlgU | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| O | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| O | MdO | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| O | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
|---|-------|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| O | rAI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
Expand Down
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