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ArchC: Architecture Description Language

A powerful open-source Architecture Description Language (ADL) based on SystemC
Automatically generates high-performance functional (500+ MIPS), compiled, and cycle-accurate processor simulators, binutils backends, and GDB debugger support from a single high-level specification.

License SystemC C++17 ELF Support Performance Platforms

📌 Overview

ArchC is an Architecture Description Language (ADL) designed to speed up the exploration, design, and validation of new processor architectures (including RISC-V, ARM, MIPS, SPARC, PowerPC, x86, 8051, or custom ASIP/DSP cores).

Instead of manually writing instruction set simulators, assemblers, linkers, and debuggers from scratch, developers describe the processor hardware resources and instruction set in two concise files:

  1. Architecture Description (<arch>.ac): Defines registers, memory hierarchy, caches, pipelines, pipeline stages, and TLM/TLM2 bus interfaces.
  2. Instruction Set Architecture (<arch>.isa): Defines instruction formats, binary encoding, decode logic, and C/C++ operational semantics for each instruction.

ArchC then automatically compiles this specification into optimized SystemC models, software development tools, and debug stubs.

🏛️ Supported Architecture Models (tests/)

ArchC includes complete, tested, and optimized processor models with native test suites:

Architecture Wordsize / Endianness Features Folder Throughput
RISC-V 32-bit (RV32I / RV64I), LE R/I/S/B/U/J formats, hardwired x0, ELF32 & ELF64 support tests/riscv/ 512+ MIPS
ARM 32-bit (ARMv7 / AArch32), LE CPSR flags (N, Z, C, V), 16 condition codes, DP, Mem, Branch tests/arm/ 380+ MIPS
MIPS 32-bit (MIPS-I / MIPS32), BE 32 GPRs, hi/lo registers, mult/div, branch delay handling tests/mips/ 514+ MIPS
SPARC 32-bit (SPARC V8), BE 32 registers (%g, %o, %l, %i), %psr condition codes tests/sparc/ 563+ MIPS
PowerPC 32-bit (PPC32), BE 32 GPRs, Condition Register (CR), Link & Count registers tests/powerpc/ 458+ MIPS
Intel x86 32-bit (i386 CISC), LE EAX–EDI, EFLAGS register, displacement addressing tests/i386/ 550+ MIPS
Intel x86-64 64-bit (AMD64 / x64), LE 16 64-bit GPRs (RAX..R15), RFLAGS, ELF64 support tests/x86_64/ 628+ MIPS
AArch64 64-bit (ARMv8-A / ARM64), LE X0–X30, XZR, PSTATE (NZCV), ELF64 support tests/aarch64/ 534+ MIPS
Apple Silicon ARM64e 64-bit (ARMv8.5-A/v9-A / M1–M4), LE Pointer Authentication (PAC pacia/autia), AMX Coprocessor (amx_fma), 512MB Unified Memory tests/apple_arm/ 536+ MIPS
DEC Alpha 64-bit (Alpha 21264 / AXP), LE 32 64-bit GPRs, CMOV, no condition codes, ELF64 support tests/alpha/ 516+ MIPS
TI C6x DSP 32-bit (TMS320C6000 VLIW), LE Dual-bank (A0..A15, B0..B15), VLIW p-bit, Saturated Math (SADD/SMPY) tests/c6x/ 505+ MIPS
ESP32 (Xtensa) 32-bit (Tensilica LX6 / WROOM), LE 16 GPRs (A0..A15), Zero-overhead loop (loop), IoT MCU tests/esp32/ 500+ MIPS
ESP32-S3 32-bit (Tensilica LX7 + AI Vector), LE Xtensa LX7 + PIE AI vector instructions (ee.vdot.s8, Q0..Q7), 8MB Octal PSRAM tests/esp32s3/ 480+ MIPS
ESP32-C3 32-bit (RISC-V RV32IMC), LE 32 GPRs (x0..x31), Hardware M-ext Multiply/Divide, CSRs tests/esp32c3/ 455+ MIPS
STM32F103 (Blue Pill) 32-bit (ARM Cortex-M3 / ARMv7-M), LE 16 GPRs (R0..R15, SP, LR), xPSR flags, Thumb/Thumb-2, 128KB Flash / 20KB SRAM tests/stm32/ 437+ MIPS
Nordic nRF52 (BLE/ULP) 32-bit (ARM Cortex-M4F / ARMv7E-M), LE 16 GPRs (R0..R15), Ultra-Low Power WFE/SEV/WFI, 1MB Flash / 256KB SRAM tests/nrf52/ 507+ MIPS
Motorola 68000 32-bit (m68k CISC), BE 8 Data (D0–D7), 8 Address (A0–A7), CCR flags, Sega/Amiga ISA tests/m68k/ 395+ MIPS
MOS 6502 8-bit CISC (NES / Apple II), BE A, X, Y, S, P, Zero-Page addressing, classic 8-bit ISA tests/m6502/ 416+ MIPS
Atmel AVR 8-bit Harvard RISC (Arduino), LE 32 registers (R0..R31), 16-bit pointers X/Y/Z, SREG tests/avr/ 438+ MIPS
Intel 8051 8-bit Harvard Architecture Separate PM/DM, ACC, PSW, DPTR, variable-length ISA tests/m8051/ 443+ MIPS
Bench32 32-bit RISC Baseline, LE Optimized baseline reference suite for profiling and bottlenecks tests/bench32/ 513+ MIPS

Run all architecture tests with a single command:

python3 tests/run_all_arch_tests.py

🍏 3. Apple Silicon (ARM64e / M1–M4) — Pointer Authentication & Matrix Coprocessor

  • Архитектура: 64-bit ARMv8.5-A / ARMv9-A (ARM64e, Little-Endian).
  • Ключевые фичи аппаратной платформы Apple:
    • Apple Pointer Authentication Code (PAC): Аппаратная защита указателей с криптографическим тегированием верхних бит адреса (pacia, autia, pacda, autda). Предотвращает ROP/JOP атаки на уровне ядра и системных сервисов.
    • Apple Matrix Coprocessor (AMX): Скрытый высокопроизводительный блок тензорных и матричных вычислений (amx_fma), разгружающий NPU и CPU при обработке нейросетей и линейной алгебры.
    • 512 MB Unified Memory (UMA) & 16 MB AMX SRAM: Сверхбыстрая общая память для параллельной обработки данных CPU и акселератором.
  • Производительность симуляции в ArchC: 536+ MIPS (~35 млн инструкций за 0.06 сек).

Смотри модель и верификационный набор: tests/apple_arm/

🏭 1. STM32 (STMicroelectronics) — Мировой стандарт №1 для промышленности и устройств

  • Архитектура: ARM Cortex-M0+ / M3 / M4 / M7 / M33 (ARMv7-M Thumb/Thumb-2, Little-Endian).
  • Популярные линейки:
    • STM32G0 / STM32C0: Копеечные чипы (от $0.3) для блоков питания, умных терморегуляторов, бытовой техники.
    • STM32F4 / STM32G4: Дроны (полетные контроллеры Betaflight), материнские платы 3D-принтеров, управление бесколлекторными двигателями, инверторы.
    • STM32H7 (до 550 МГц, 2 ядра): Промышленная робототехника, осциллографы, сложная цифровая обработка сигналов (DSP).
    • STM32WL (со встроенным радиочипом LoRa): Дальнобойные беспроводные счетчики (передача данных на 10–15 км).
  • Почему в проде: Железная устойчивость к помехам (EMC/ESD), гарантия выпуска одного и того же чипа на 10–15 лет вперед (Longevity Commitment), профессиональная среда отладки.

Смотри модель и верификационный набор: tests/stm32/

🔋 2. Nordic Semiconductor (nRF52 / nRF53 / nRF91) — Короли автономности и Bluetooth (BLE)

  • Архитектура: ARM Cortex-M4F / Cortex-M33 (ARMv7E-M Thumb-2 + ULP Event Control, Little-Endian).
  • Популярные чипы:
    • nRF52840 / nRF52832: Флагманы Bluetooth Low Energy (BLE 5.0), Thread, Zigbee, ANT, 2.4 GHz RF.
    • nRF5340: Двухъядерный чип (Application Core Cortex-M33 + Network Core Cortex-M33) для аудиоустройств нового поколения (LE Audio).
    • nRF9160: Сверхмалопотребляющий SiP со встроенным модемом LTE-M / NB-IoT и GPS.
  • Главный козырь: Сверхнизкое энергопотребление (Ultra-Low Power):
    • ESP32 в режиме сна и пробуждения тратит много энергии — на батарейке проработает пару месяцев.
    • Чипы Nordic на одной маленькой батарейке-таблетке CR2032 работают 3–5 ЛЕТ!
  • Где стоят: Беспроводные мыши/клавиатуры (Logitech), фитнес-браслеты, медицинские глюкометры и пульсоксиметры, метки-трекеры (аналоги Apple AirTag), умные дверные замки.

Смотри модель и верификационный набор: tests/nrf52/

🚀 Key Features & Innovations

  • High-Performance Direct Threading Engine:
    • Direct threading simulation with GCC computed gotos and decode caching (DEC_CACHE).
    • Single-word fast-path in GetBits(): Bypasses multi-word loop allocations for standard instructions.
    • $O(1)$ Direct Table Indexing in Decoder: Eliminated linear linked-list traversal during runtime decoding.
  • Native 64-bit ELF (ELF64) Loader:
    • Full support for ELFCLASS64 and ELFCLASS32 binaries with automatic Big/Little-Endian conversion.
  • Multiple Simulator Generators:
    • acsim (Interpreted Simulator): Rapid turnaround instruction set simulator (ISS) with full trace logs and debugging support.
    • accsim (Compiled Simulator): High-speed static binary translation to C++ for ultra-fast architectural simulation.
    • actsim (Cycle-Accurate / Timed Simulator): Captures pipeline stages, resource hazards, stalls, and multi-cycle execution delays.
  • GNU Binutils Generation (src/acbinutils): Generates target-specific assembler (as), disassembler (objdump), and linker (ld) backends.
  • GDB Remote Debugging: Built-in GDB remote serial protocol server allowing native GDB sessions to step, breakpoint, and inspect simulated cores.
  • Power Estimation (PowerSC): Energy and power consumption estimation module using macro-models during SystemC simulation.
  • SystemC & TLM 2.0 Integration: Native Transaction-Level Modeling (TLM 1.0 and TLM 2.0) for building virtual platforms and SoC models.

🔄 Simulation Workflow

flowchart TD
    subgraph ArchC Specification
        A["Architecture Model<br/><b>arch.ac</b>"]
        B["Instruction Semantics<br/><b>arch.isa</b>"]
    end

    subgraph ArchC Framework
        C["ArchC Engine<br/><code>acsim</code> / <code>accsim</code> / <code>actsim</code>"]
        D["GNU Binutils Backend<br/><code>bmdsfg</code>"]
    end

    subgraph Generated Artifacts
        E["C++ / SystemC Model<br/><code>arch.cpp</code>, <code>arch.H</code>, <code>Makefile.archc</code>"]
        F["Assembler / Linker<br/><code>as</code>, <code>ld</code>, <code>objdump</code>"]
    end

    subgraph Execution & Debugging
        G["Compiled Simulator<br/><b>arch.x</b>"]
        H["Application Binary<br/><code>program.elf</code> / <code>program.hex</code>"]
        I["Simulation Results & Traces"]
        J["GDB Remote Debugger"]
    end

    A --> C
    B --> C
    A --> D
    B --> D

    C --> E
    D --> F

    E -- make --> G
    H --> G
    G --> I
    G <--> J
Loading

📦 Project Structure

Component Path Description
acsim src/acsim/ Interpreted simulator generator
accsim src/accsim/ Compiled simulator generator
actsim src/actsim/ Cycle-accurate / timed simulator generator
acbinutils src/acbinutils/ Binutils code generator & relocation converter
aclib src/aclib/ Core runtime library (registers, memory, caches, TLM ports, syscalls)
acpp src/acpp/ ArchC language preprocessor, parser (Flex/Bison), and AST builder
powersc src/powersc/ Power and energy estimation library
tests tests/ Ready-to-use processor models (RISC-V, ARM, MIPS, SPARC, PPC, x86, 8051)
bin bin/ User helper scripts (ac_run, ac_model, ac_stat, set_env)
doc doc/ Developer guides, TLM how-to, and migration documents

🛠️ Requirements & Installation

Prerequisites

  • GNU Autotools: autoconf (>= 2.59), automake (>= 1.14), libtool / glibtoolize, pkg-config, m4, make
  • Parsers: flex and bison
  • Compiler: C/C++ compiler supporting C++17 (clang++ or g++)
  • SystemC: SystemC >= 2.3.0 (including 3.0.x) with TLM 2.0 support
  • Optional: elfutils (libelf, libdw) for High Level Trace (HLT)

macOS (Homebrew)

brew install systemc pkg-config autoconf automake libtool flex bison

Linux (Ubuntu / Debian / Fedora)

# Ubuntu / Debian
sudo apt-get update
sudo apt-get install build-essential autoconf automake libtool pkg-config flex bison libsystemc-dev

# Fedora / RHEL
sudo dnf install autoconf automake libtool pkgconfig flex bison systemc-devel

⚙️ Configuration & Building

1. Generate Build Scripts

./autogen.sh

2. Configure

./configure --prefix=$(pwd)/install_local

Common Configuration Flags:

Flag Description
--prefix=<dir> Installation directory
--with-systemc=<dir> Path to custom SystemC installation
--with-binutils=<dir> Path to GNU Binutils source directory
--with-gdb=<dir> Path to GNU GDB source directory
--disable-hlt Disable High Level Trace feature (if libelf is not installed)

3. Compile & Install

# macOS
make -j$(sysctl -n hw.ncpu) && make install

# Linux
make -j$(nproc) && make install

💻 Quickstart: Creating & Running a Model

1. Define Architecture (riscv.ac)

AC_ARCH(riscv) {
  ac_mem            DM:512M;           // 512MB address space
  ac_regbank        RB:32;             // 32 integer registers
  ac_wordsize       32;
  ac_fetchsize      32;

  ARCH_CTOR(riscv) {
    ac_isa("riscv.isa");               // Link ISA specification
    set_endian("little");
  };
};

2. Define Instructions (riscv.isa)

AC_ISA(riscv) {
  ac_format Type_R = "%funct7:7 %rs2:5 %rs1:5 %funct3:3 %rd:5 %opcode:7";
  ac_instr<Type_R> add, sub;

  ISA_CTOR(riscv) {
    add.set_asm("add %rd, %rs1, %rs2");
    add.set_decoder(opcode = 0x33, funct3 = 0x0, funct7 = 0x00);
  };
};

3. Implement Behavior (riscv_isa.cpp)

void ac_behavior( add ) {
  RB[rd] = RB[rs1] + RB[rs2];
  RB[0] = 0; // x0 hardwired to 0
}

4. Build and Run Simulator

acsim riscv.ac -nw -nci
make -f Makefile.archc -j$(sysctl -n hw.ncpu)
./riscv.x --load=program.elf

⚡ Benchmarking & Performance Profiling

Run the complete multi-architecture verification testbench:

python3 tests/run_all_arch_tests.py

Performance Summary (on Apple Silicon ARM64, SystemC 3.0.2):

  • ALU Throughput: 500–583 MIPS across all models.
  • Memory Operations (LW/SW): 340–400 MIPS.
  • Branch / Control Flow: 360–370 MIPS.
  • Decode Cache Advantage: 18× speedup over on-the-fly decoding (-ndc).
  • Detailed architectural analysis available in tests/bench32/README.md.

📜 License & Academic Credits

  • ArchC Tools are licensed under the GNU General Public License (GPL) v2. See COPYING.
  • ArchC Utility Library (src/aclib) is licensed under the GNU Lesser General Public License (LGPL) v2. See COPYING.LIB.

Developed by:
Computer Systems Laboratory (LSC)
Institute of Computing (IC)
University of Campinas (UNICAMP), Brazil
http://www.lsc.ic.unicamp.br

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A powerful and modern open-source architecture description language.

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