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v1.0.0

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@bmatiasruben bmatiasruben released this 19 Mar 22:54
· 46 commits to main since this release
v1.0.0
d91b26a

First release

First complete version of the system, including:

  • 8 transceiver channels for pulse generation, up to 10 pulses (software limitation, easily modifiable)
  • 10 MHz clock output coming out of CLK1_M2C of FMC port HMC1 of the ZCU102
  • Reset GPIO (not implemented on PYNQ yet) that allows re-synchronization of channels in case of changing period
  • No loss of phase locking when modifying settings (except period; phase-locking is still lost there)

With the new release. I am adding here the binaries for the bitstream and the hardware hand-off obtained by Vivado, to then place into the Pynq directory within the FPGA.

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