Feature: 10 MHz clk out locked independent of rate

Modified the input reference clock for generating the 10 MHz clock out. Now it depends on the REFCLK of the transceivers instead of the txusrclk that changes with the rate.

Feature: Lock to external 10 MHz

Added capability to lock to an external 10 MHz clock and automatically switch to using that if seen. Otherwise system works as before. Breaking changes since clock ports are changed.

Feature: Added pre-emphasis and voltage control

Added 3 GPIO controls to set precursor, postcursor and diffctrl ports of the Transceiver Wizard IP. They allow to control the output amplitude from couple mVpp to around 1 Vpp. They also allow for some extra pulse shaping capabilites.

Fix: reset GPIO was wrong level

Same as before, but this time the reset associated to the reset GPIO is defined as active_high, as it should've been from the beginning. With the previous release, when compiling the Overlay, Ubuntu crashed.

v1.0.0

First release

First complete version of the system, including:

• 8 transceiver channels for pulse generation, up to 10 pulses (software limitation, easily modifiable)
• 10 MHz clock output coming out of CLK1_M2C of FMC port HMC1 of the ZCU102
• Reset GPIO (not implemented on PYNQ yet) that allows re-synchronization of channels in case of changing period
• No loss of phase locking when modifying settings (except period; phase-locking is still lost there)

With the new release. I am adding here the binaries for the bitstream and the hardware hand-off obtained by Vivado, to then place into the Pynq directory within the FPGA.