Release v1.5.3

What's Changed

• fix: XML width, HTML type/default/port-direction correctness by @bugratufan in #121
• release: v1.5.2 feature and bug fix batch by @bugratufan in #122

Full Changelog: v1.5.2...v1.5.3

Release v1.5.2

What's Changed

• fix(sv_generator): register width ignored in SV output when using YAML input (#117) by @bugratufan in #118
• fix(sv_generator): register width ignored in SV output when using YAML input (#117) by @bugratufan in #119

Full Changelog: v1.5.1...v1.5.2

Release v1.5.1

What's Changed

• fix: CLI help on no args, readthedocs URL, and About button link by @bugratufan in #115
• fix: CLI UX improvements and HTML doc link fixes by @bugratufan in #116

Full Changelog: v1.5.0...v1.5.1

Release v1.5.0

What's Changed

• feat(register-model): Python register space model and *_regs.py generator by @bugratufan in #112
• feat(hier): canonical entry + named instances support (HIER-017–021) by @bugratufan in #113
• feat: Python register model + hierarchy canonical instance support by @bugratufan in #114

Full Changelog: v1.4.0...v1.5.0

Release v1.4.0

What's Changed

• feat: add --hier flag for centralized base address assignment by @bugratufan in #109
• feat: hierarchy support, logo branding and HTML report improvements by @bugratufan in #110

Full Changelog: v1.3.0...v1.4.0

Release v1.3.0

What's Changed

• feat: add enumerated values support for register bit fields by @bugratufan in #103
• feat(gui): add beta warning popup on session start by @bugratufan in #106
• feat: typed AXI port generation via axion_common_pkg (AXION-TYPES-001..021) by @bugratufan in #107
• release: merge develop into main — enum values, typed AXI ports, GUI beta warning by @bugratufan in #108

Full Changelog: v1.2.1...v1.3.0

Release v1.2.1

What's Changed

• sync: main → develop (CI fix) by @bugratufan in #100
• fix: handle None default_value from SV parser by @bugratufan in #101
• fix: SV default_value None handling and CI publish fix by @bugratufan in #102

Full Changelog: v1.2.0...v1.2.1

Release v1.2.0

What's Changed

• feat(sv): add SystemVerilog support by @bugratufan in #98
• feat: SystemVerilog support (parse, generate, GUI, CI) by @bugratufan in #99

Full Changelog: v1.1.3...v1.2.0

Release v1.1.3

What's Changed

• Update documentation and add TOML support by @bugratufan in #93
• fix(parser): allow bare @Axion annotations and recover from address conflicts by @bugratufan in #96
• fix(parser): allow bare @Axion annotations and recover from address conflicts by @bugratufan in #97

Full Changelog: v1.1.2...v1.1.3

Release v1.1.2

What's Changed

• feat: Implement numeric validation and generation safety locks by @bugratufan in #91
• Release v1.1.2: Enhanced Validation and Parser Robustness by @bugratufan in #92

Full Changelog: v1.1.1...v1.1.2