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Some chips have PCINT setups that are not aligned with ports.
For example, the 2560 has PCINT8 on E0, and PCINT9-15 on J0-6

This adds a mask and shift option to the PCINT declaration to support this.

The default mask behaviour is that if mask = 0 (no PCINTs, this doesn't make sense in a normal context) then the behaviour is as before. If mask and/or shift are defined, the bitfield is shifted appropriately to align it with the expectation for the & with irq->irq.

Also includes a fix for PORTJ on the 2560 to enable its PCINTs using this.

@buserror buserror merged commit 1ce3462 into buserror:master Aug 3, 2020
fengjixuchui added a commit to fengjixuchui/simavr that referenced this pull request Aug 3, 2020
Merge pull request buserror#390 from vintagepc/unaligned-PCINTs
@vintagepc vintagepc deleted the unaligned-PCINTs branch August 3, 2020 23:18
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2 participants