Skip to content

Support for non-aligned PCINTs #390

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Aug 3, 2020
Merged

Support for non-aligned PCINTs #390

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 12 additions & 2 deletions simavr/cores/sim_mega2560.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,17 @@ const struct mcu_t {
AVR_IOPORT_DECLARE(f, 'F', F),
AVR_IOPORT_DECLARE(g, 'G', G),
AVR_IOPORT_DECLARE(h, 'H', H),
AVR_IOPORT_DECLARE(j, 'J', J),
.portj = {
.name = 'J', .r_port = PORTJ, .r_ddr = DDRJ, .r_pin = PINJ,
.pcint = {
.enable = AVR_IO_REGBIT(PCICR, PCIE1),
.raised = AVR_IO_REGBIT(PCIFR, PCIF1),
.vector = PCINT1_vect,
.mask = 0b11111110,
.shift = -1
},
.r_pcint = PCMSK1,
},
AVR_IOPORT_DECLARE(k, 'K', K),
AVR_IOPORT_DECLARE(l, 'L', L),

Expand Down Expand Up @@ -353,7 +363,7 @@ const struct mcu_t {
.r_tcnt = TCNT2,
// asynchronous timer source bit.. if set, use 32khz frequency
.as2 = AVR_IO_REGBIT(ASSR, AS2),

.overflow = {
.enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
.raised = AVR_IO_REGBIT(TIFR2, TOV2),
Expand Down
14 changes: 12 additions & 2 deletions simavr/sim/avr_ioport.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -153,7 +153,18 @@ avr_ioport_irq_notify(

if (p->r_pcint) {
// if the pcint bit is on, try to raise it
int raise = avr->data[p->r_pcint] & mask;
int raisedata = avr->data[p->r_pcint];
uint8_t uiRegMask = p->pcint.mask;
int8_t iShift = p->pcint.shift;
if (uiRegMask) // If mask is 0, do nothing (backwards compat)
raisedata &= uiRegMask; // Mask off

if (iShift>0) // Shift data if necessary for alignment.
raisedata <<= iShift;
else if (iShift<0)
raisedata >>= -iShift;

int raise = raisedata & mask;
if (raise)
avr_raise_interrupt(avr, &p->pcint);
}
Expand Down Expand Up @@ -279,4 +290,3 @@ void avr_ioport_init(avr_t * avr, avr_ioport_t * p)
avr_register_io_write(avr, p->r_pin, avr_ioport_pin_write, p);
avr_register_io_write(avr, p->r_ddr, avr_ioport_ddr_write, p);
}

3 changes: 3 additions & 0 deletions simavr/sim/sim_interrupts.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,9 @@ typedef struct avr_int_vector_t {
avr_regbit_t enable; // IO register index for the "interrupt enable" flag for this vector
avr_regbit_t raised; // IO register index for the register where the "raised" flag is (optional)

uint8_t mask; // Mask for PCINTs. this is needed for chips like the 2560 where PCINT do not align with IRQs
int8_t shift; // PCINT8 = E0, PCINT9-15 are on J0-J6. Shift shifts down (<0) or up (>0) for alignment with IRQ#.

// 'pending' IRQ, and 'running' status as signaled here
avr_irq_t irq[AVR_INT_IRQ_COUNT];
uint8_t pending : 1, // 1 while scheduled in the fifo
Expand Down