Toon Syntax Reference

Table of Contents Syntax Reference Notes Register Based Assignment Statements Delay Memory Load/Store/Interpolate 32 Bit Operations 64 Bit Summing Math Operations Conditional Branching Effects Instructions Other Instructions

Syntax Reference Notes

• <abc> substitute with an appropriate value (register, renamed symbol, constant, etc)
• (x) indirect addressing of delay memory, including address counter (AGU)
• #(x) absolute indirect addressing of delay memory (no AGU)
• [x] indirect addressing of memory registers
• Use of all CAPS in the syntax indicate literals, e.g. ACC32 means it must be exactly that text
• CR Core Register - R0-R15, ACC32, FLAGS (does not include ACC64)
• MR Memory Register - MR0-MR127
• SFR Special Function Register - INx, OUTx, BOOTSTAT, etc. see FXCore documentation
• Some statements infer the proper mnemonic based on the types of the operands
• Currently IF statement tokens must be space or tab separated, e.g. if r6>=0 goto mylabel is not valid, must be if r6 >= 0 goto mylabel

Register Based Assignment Statements

These are assignment statements that copy data from one register to another. An FXCore 'register' may a Core Register (CR), Memory Register (MR) or Special Function Register (SFR). TOON only allows assignments for which there exists a single FXCore instruction that can implement it. E.g. it is not possible to move data between Memory Registers with a single instruction, thus the assignment MR6 = MR29 is invalid and would be flagged as an error.

Syntax	Examples	Notes	Generated
<targetReg> = <sourceReg>	acc32 = r8 r2 = mr102 r0 = switch mr106 = acc32	Copy between CR, MR, and SFR Proper cpy_xx instruction will be inferred Supported combinations CR = CR CR = MR CR = SFR MR = CR SFR = CR	cpy_cc cpy_cm cpy_cs cpy_mc cpy_sc
<targetCR> = [<sourceCR>]	r0 = [acc32]	Indirect addressing of MR by source register	cpy_cmx
<cr>.U = <const>	r0.u = 0xFF	Copy 16 bit immediate value to upper half of CR and zero lower half	wrdld
acc32 = 0	acc32 = 0	Zero all bits of ACC32.	xor
<cr> = ACC64.U <cr> = ACC64.L <cr> = ACC64.SAT ACC64.U = <cr> ACC64.L = <cr>	r4 = acc64.u acc64.l = acc32	Copy upper/lower 32 bits of ACC64 to/from a CR	rdacc64u rdacc64l sat64 ldacc64u ldacc64l

Delay Memory Load/Store/Interpolate

These assignment statements move data between Core Registers and the FXCore delay memory. Data can be read or written by constant address, by an address contained in a CR ("indirect" addressing) or by an absolute address in a CR ("absolute indirect" addressing).

Syntax	Examples	Notes	Generated
<cr> = (<const>) (<const>) = <cr> <cr> = (<cr>) (<cr>) = <cr> <cr> = #(<cr>) #(<cr>) = <cr>	r4 = (2487) (2487) = r4 r0 = (r5) (r5) = r0 r0 = #(r5) #(r5) = r0	Load/store delay memory By address (const) By indirect reg (cr) By absolute indirect reg #(cr)	rddel wrdel rddelx wrdelx rddirx wrdirx
ACC32 = interp (<cr>+<const>)	acc32 = interp (r5+200)	Operand is indirect address from CR plus a constant	interp

32 Bit Operations

The following are assignment statements that update the ACC32 Core Register by application of a function (FXCore instruction) to 2 operands. FXCore has a range of 32-bit functions including bitwise logic, shifting, add, subtract, and multiply. Some functions have different variations depending on the operand type (constant or register), and variations for logical versus arithmetic/saturating functions. In all there are 22 different FXCore mnemonics for 7 basic functions (add, subtract, multiply, and, or, xor, shift).

TOON simplifies the 32-bit functions with common programming symbols like + for ADD, * for multiply, etc. TOON will examine the operand types and automatically infer the correct FXCore instruction variation (see Inferred Instructions). Using the symbols instead of FXCore assembler mnemonics reduces the amount of detail required (e.g. ADD vs ADDI vs ADDS vs ADDSI) making the source code simpler and more intuitive to read (and don't have to remember all those similar-but-different mnemonics).

Although use of the symbols is recommended, these assignment statements allow direct use of any valid FXCore 32-bit operation mnemonic as the function if that form is preferred.

Syntax	Examples	Notes
ACC32 = <op1> <function> <op2>	Symbol Examples ACC32 = R0 & 0x04 ACC32 = R0 >> 2 ACC32 = R0 <<< R1 ACC32 = R0 + R1 ACC32 = R0 -- R1 ACC32 = ACC32 ^ 0xF0 ACC32 = ACC32 * 0.1 Mnemonic Examples ACC32 = r0 xori 0x04 ACC32 = R0 sr 2 ACC32 = R0 slsr R1 ACC32 = R0 add R1 ACC32 = R0 subs R1 ACC32 = ACC32 xori 0xF0 ACC32 = ACC32 multri 0.1 Immediate or Register inferred by operand type ACC32 = r0 | 0x7 ACC32 = r0 | r7	Symbol Functions + : Add ++ : Add arithmetic - : Subtract -- : Subtract arithmetic * : Multiply | : Bitwise OR & : Bitwise AND ^ : Bitwise XOR << : Shift left logical <<< : Shift left saturating >> : Shift right logical >>> : Shirt right arithmetic Mnemonic Functions ADDI ADD ADDS ADDSI SUB SUBS MULTRR MULTRI SL SLR SLS SLSR SR SRR SRA SRAR OR ORI AND ANDI XOR XORI
ACC32 = <instr> <cr>	acc32 = neg R6 acc32 = inv acc32	Supported instructions INV ABS NEG LOG2 EXP2

64 Bit Summing Math Operations

Syntax	Examples	Notes
ACC64 += <op1> <instr> <op2>	acc64 += R0 macrr R1 acc64 += R8 machri -0.7	Use '+=' or '=' assignment operator Supported instructions MACRR MACRI MACR (infers MACRR or MACRI) MACRD MACID MACD (infers MACID or MACRD) MACHRR MACHRI MACHR (infers MACHRR or MACHRI) MACHRD MACHID MACHD (infers MACHRD or MACHID)

Conditional Branching

The 3 basic forms of writing conditional execution logic in TOON are described in the table below - unconditional GOTO statements, conditional branching with IF ... GOTO statements, and IF ... THEN ... ELSE... ENDIF code blocks. Only IF...THEN style conditionals (must) be terminated with an ENDIF statement. See Conditional Branching for more information on TOON conditional execution statements.

Syntax	Examples	Notes	Generated
JMP <label> GOTO <label>	goto mylabel	Unconditional branch. JMP and GOTO are synonyms.	jmp
IF <cr> <cond> 0|ACC32.SIGN [GOTO] <label>	if r7 >= 0 goto mylabel if r1 = 0 mylabel if acc32 < 0 mylabel if r0 != 0 goto mylabel if r2 != acc32.sign mylabel	Conditions • = 0 • <> 0 • != 0 • != ACC32.SIGN • >= 0 • < 0	jz jnz jgez jneg jzc
IF <cr> <cond> 0|ACC32.SIGN [THEN] ; Do this if <cond> is true [ELSE] ; Do this if <cond> is false ENDIF	if r5 != 0 then acc32 = r0 acc32 = acc32 sr 2 else acc32 = r1 acc32 = acc32 sl 2 endif if acc32 = 0 then r1 = r10 else r1 = r11 endif if r2 > 0 then acc32 = r2 sr 1 out1 = acc32 endif	Conditions • = 0 • <> 0 • != 0 • = ACC32.SIGN • >= 0 •* < 0	jz jnz jgez jneg jzc
IF <cr> <cond> 0|ACC32.SIGN THEN <stmt>	if acc32 < 0 then acc32 = 0	Special form of single line IF-THEN-stmt has no ELSE and no ENDIF.

Effects Instructions

Syntax	Examples	Generated
See Chorus Instruction General form: ACC32,R15 = CHORUS <depth>, LFO[0|1|2|3], [+|-]SIN|COS, (const-addr) depth may be CR, MR, or constant R15 is omitted from left side when depth is R15 Specific forms: ACC32,R15 = CHORUS <depthCR>, <LFOn>, [+|-]<SIN|COS>, (<const-addr>) ACC32,R15 = CHORUS <depthMR>, <LFOn>, [+|-]<SIN|COS>, (<const-addr>) ACC32,R15 = CHORUS <depthConst>, <LFOn>, [+|-]<SIN|COS>, (<const-addr>) ACC32 = CHORUS r15, <LFOn>, [+|-]<SIN|COS>, (<const-addr>)	acc32,r15 = chorus 128, lfo2, -cos, (membuff) acc32,r15 = chorus r4, lfo1, sin, (200)	chr
See All Pass Filter Instruction General form: ACC32,R15 = ACC32 ALLPASS <coeff>, <head>, <tail> Specific forms: ACC32,R15 = ACC32 ALLPASS <cont-coeff>, (<head-addr>), (<tail-addr>) ACC32,R15 = ACC32 ALLPASS <cr-coeff>, (<head-addr>), (<tail-addr>) ACC32,R15 = ACC32 ALLPASS <cr-coeff>, (<CR-addr-head>), (<CR-addr-tail>) ACC32,R15 = ACC32 ALLPASS <cr-coeff>, <MR>	Constant head/tail addresses: acc32,r15 = acc32 allpass 0.44, (200), (300) acc32,r15 = acc32 allpass r12, (membuff), (membuff#) Indirect head/tail addresses via CRs: acc32,r15 = acc32 allpass r12, (r0), (r1) Single delay element in MR: acc32,r15 = acc32 allpass r12, mr110	apa apb apra aprb aprra aprrb apma apmb

Other Instructions

There are not currently TOON statements for the remainder of the FXCore instruction set. The following instructions should be coded in regular FXCore assembler format.

pitch rmp0|L4096, 4096
set user0|15, r0