Toon Syntax Reference

Table of Contents Syntax Reference Notes Register Based Assignment Statements Delay Memory Load/Store/Interpolate 32 Bit Operations 64 Bit Summing Math Operations Conditional Branching Effects Instructions Other Instructions

Syntax Reference Notes

• <abc> substitute with an appropriate value (register, renamed symbol, constant, etc)
• (x) indirect addressing of delay memory, including address counter (AGU)
• #(x) absolute indirect addressing of delay memory (no AGU)
• [x] indirect addressing of memory registers
• Use of all CAPS in the syntax indicate literals, e.g. ACC32 means it must be exactly that text
• CR Core Register - R0-R15, ACC32, FLAGS (does not include ACC64)
• MR Memory Register - MR0-MR127
• SFR Special Function Register - INx, OUTx, BOOTSTAT, etc. see FXCore documentation
• Some statements infer the proper mnemonic based on the types of the operands
• Currently IF statement tokens must be space or tab separated, e.g. if r6>=0 goto mylabel is not valid, must be if r6 >= 0 goto mylabel

Register Based Assignment Statements

These are assignment statements that copy data from one register to another. An FXCore 'register' may a Core Register (CR), Memory Register (MR) or Special Function Register (SFR). TOON only allows assignments for which there exists a single FXCore instruction that can implement it. E.g. it is not possible to move data between Memory Registers with a single instruction, thus the assignment MR6 = MR29 is invalid and would be flagged as an error.

Syntax	Examples	Notes	Generated
<targetReg> = <sourceReg>	acc32 = r8 r2 = mr102 r0 = switch mr106 = acc32	Copy between CR, MR, and SFR Proper cpy_xx instruction will be inferred Supported combinations CR = CR CR = MR CR = SFR MR = CR SFR = CR	cpy_cc cpy_cm cpy_cs cpy_mc cpy_sc
<targetCR> = [<sourceCR>]	r0 = [acc32]	Indirect addressing of MR by source register	cpy_cmx
<cr>.U = <const>	r0.u = 0xFF	Copy 16 bit immediate value to upper half of CR	wrdld
acc32 = 0	acc32 = 0	Zero all bits of ACC32.	xor
<cr> = ACC64.U <cr> = ACC64.L <cr> = ACC64.SAT ACC64.U = <cr> ACC64.L = <cr>	r4 = acc64.u acc64.l = acc32	Copy upper/lower 32 bits of ACC64 to/from a CR	rdacc64u rdacc64l sat64 ldacc64u ldacc64l

Delay Memory Load/Store/Interpolate

These assignment statements move data between Core Registers and the FXCore delay memory. Data can be read or written by constant address, by an address contained in a CR ("indirect" addressing) or by an absolute address in a CR ("absolute indirect" addressing).

Syntax	Examples	Notes	Generated
<cr> = (<const>) (<const>) = <cr> <cr> = (<cr>) (<cr>) = <cr> <cr> = #(<cr>) #(<cr>) = <cr>	r4 = (2487) (2487) = r4 r0 = (r5) (r5) = r0 r0 = #(r5) #(r5) = r0	Load/store delay memory By address (const) By indirect reg (cr) By absolute indirect reg #(cr)	rddel wrdel rddelx wrdelx rddirx wrdirx
ACC32 = interp (<cr>+<const>)	acc32 = interp (r5+200)	Operand is indirect address from CR plus a constant	interp

32 Bit Operations

The following are assignment statements that update the ACC32 Core Register by application of a function (FXCore instruction) to 2 operands. FXCore has a wide range of 32-bit functions including bitwise logic, shifting, add, subtract, and multiply. Some functions have different variations depending on the type (constant or register) of the operations. If the function names OR, AND, XOR, SL, SR, or MULT are used, TOON will examine the operand types and automatically infer the correct FXCore instruction (see Inferred Instructions).

Syntax	Examples	Notes
ACC32 = <op1> <instr> <op2>	ACC32 = r0 xor r0 ACC32 = r0 and r1 ACC32 = r0 andi 0x7 ACC32 = r10 and 5 + 2 ACC32 = r1 multri 0.4 ACC32 = r1 mult r2 Immediate or Register inferred by operand type ACC32 = r0 or 0x7 ACC32 = r0 sl r7	Math instructions ADDI ADD ADDS ADDSI SUB SUBS MULTRR MULTRI Shift instructions SL SLR SLS SLSR SR SRR SRA SRAR Logic instructions OR ORI AND ANDI XOR XORI Inferred OR AND XOR SL SR MULT
ACC32 = <instr> <cr>	acc32 = neg R6 acc32 = inv acc32	Supported instructions INV ABS NEG LOG2 EXP2

64 Bit Summing Math Operations

Syntax	Examples	Notes
ACC64 += <op1> <instr> <op2>	acc64 += R0 macrr R1 acc64 += R8 machri -0.7	Use '+=' or '=' assignment operator Supported instructions MACRR MACRI MACR (infers MACRR or MACRI) MACRD MACID MACD (infers MACID or MACRD) MACHRR MACHRI MACHR (infers MACHRR or MACHRI) MACHRD MACHID MACHD (infers MACHRD or MACHID)

Conditional Branching

There are 3 basic forms of writing branch ("IF" logic) in TOON. The simplest is the unconditional GOTO which is just a synonym for the FXCore assembler JMP instruction. Conditional branching can be done in an IF ... GOTO form which is much more readable form of the FXCore test-and-branch instructions, or a more high level language-like form of IF ... THEN ... ELSE... ENDIF blocks which formulate all the FXCore testing, branching, and labels to build a complete IF-THEN-ELSE style of code. Such blocks can be nested to any level.

Note that the conditions supported by TOON are only those that can be implemented in a single FXCore branch instruction as indicated in the Notes column below.

Syntax	Examples	Notes	Generated
JMP <label> GOTO <label>	goto mylabel	Unconditional branch. JMP and GOTO are synonyms.	jmp
IF <cr> <cond> 0|ACC32.SIGN [GOTO] <label>	if r7 >= 0 goto mylabel if r1 = 0 mylabel if acc32 < 0 mylabel if r0 != 0 goto mylabel if r2 != acc32.sign mylabel	Conditions = 0 <> 0 != 0 != acc32.sign >= 0 < 0	jz jnz jgez jneg jzc
IF <cr> <cond> 0|ACC32.SIGN [THEN] ; Do this if <cond> is true ELSE ; Do this if <cond> is false ENDIF	if r5 != 0 then acc32 = r0 acc32 = acc32 sr 2 else acc32 = r1 acc32 = acc32 sl 2 endif if acc32 = 0 then r1 = r10 else r1 = r11 endif if r2 > 0 then r2 = r2 sr 1 endif	Conditions = 0 <> 0 != 0 != acc32.sign >= 0 < 0	jz jnz jgez jneg jzc

Effects Instructions

Syntax	Examples	Generated
Chorus General form: ACC32,R15 = ACC32 CHORUS <depth>, LFO[0|1|2|3], [+|-]SIN|COS, (const-addr) depth may be CR, MR, or constant	acc32,r15 = acc32 chorus 128, lfo2, -cos, (membuff) acc32,r15 = acc32 chorus r4, lfo1, sin, (200)	chr
All-Pass Filter General form: ACC32,R15 = ACC32 ALLPASS <coeff>, <head>, <tail> Specific forms: ACC32,R15 = ACC32 ALLPASS <cont-coeff>, (<head-addr>), (<tail-addr>) ACC32,R15 = ACC32 ALLPASS <cr-coeff>, (<head-addr>), (<tail-addr>) ACC32,R15 = ACC32 ALLPASS <cr-coeff>, (<CR-addr-head>), (<CR-addr-tail>) ACC32,R15 = ACC32 ALLPASS <cr-coeff>, <MR>	Constant head/tail addresses: acc32,r15 = acc32 allpass 0.44, (200), (300) acc32,r15 = acc32 allpass r12, (membuff), (membuff#) Indirect head/tail addresses via CRs: acc32,r15 = acc32 allpass r12, (r0), (r1) Single delay element in MR: acc32,r15 = acc32 allpass r12, mr110	apa apb apra aprb aprra aprrb apma apmb

Other Instructions

There are not currently TOON statements for the remainder of the FXCore instruction set. The following instructions should be coded in regular FXCore assembler format.

pitch rmp0|L4096, 4096
set user0|15, r0