Toon Syntax Reference

Syntax Reference Notes

• <abc> substitute with an appropriate value (register, renamed symbol, constant, etc)
• (x) indirect addressing of delay memory, including address counter (AGU)
• @(x) absolute indirect addressing of delay memory (no AGU)
• [x] indirect addressing of memory registers
• Use of all CAPS in the syntax indicate literals, e.g. ACC32 means it must be exactly that text
• CR Core Register - R0-R15, ACC32, FLAGS (does not include ACC64)
• MR Memory Register - MR0-MR127
• SFR Special Function Register - INx, OUTx, BOOTSTAT, etc. FXCore documentation
• Some statements infer the proper mnemonic based on the types of the operands

Register Based Copy Statements
<targetReg> = <sourceReg>	acc32 = r8</code> r2 = mr102</code> r0 = switch</code> mr106 = acc32	Copy between CR, MR, and SFR Proper cpy_xx instruction will be inferred Supported combinations CR = CR CR = MR CR = SFR MR = CR SFR = CR	Generated cpy_cc cpy_cm cpy_cs cpy_mc cpy_sc
<targetCR> = [<sourceCR>]	r0 = [acc32]	Indirect addressing of MR by source register	Generated cpy_cmx
<cr>.U = <const>	r0.u = 0xFF	Copy 16 bit immediate value to upper half of CR	Generated wrdld
<cr> = ACC64.U</code> <cr> = ACC64.L</code> <cr> = ACC64.SAT</code> ACC64.U = <cr> ACC64.L = <cr>	r4 = acc64.u acc64.l = acc32	Copy upper/lower 32 bits of ACC64 to/from a CR	Generated rdacc64u rdacc64l sat64 ldacc64u ldacc64l
Delay Memory Load/Store
<cr> = (<const>) (<const>) = <cr> <cr> = (<cr>) (<cr>) = <cr> <cr> = @(<cr>) @(<cr>) = <cr>	r4 = (2487) (2487) = r4 r0 = (r5) (r5) = r0 r0 = @(r5) @(r5) = r0	Load/store delay memory By address (const) By indirect reg (cr) By absolute indirect reg @(cr)	Generated rddel wrdel rddelx wrdelx rddirx wrdirx
32 Bit Operations
ACC32 = <op1> <instr> <op2>	ACC32 = r0 xor r0 ACC32 = r0 and r1 ACC32 = r0 andi 0x7 ACC32 = r10 and 5 + 2 ACC32 = r1 multri 0.4 ACC32 = r1 mult r2 Immediate or Register inferred by operand type ACC32 = r0 or 0x7 ACC32 = r0 sl r7	Math instructions ADDI ADD ADDS ADDSI SUB SUBS MULTRR MULTRI Shift instructions SL SLR SLS SLSR SR SRR SRA SRAR Logic instructions OR ORI AND ANDI XOR XORI Inferred OR AND XOR SL SR MULT
ACC32 = <instr> <cr>	acc32 = neg R6	Supported instructions INV ABS NEG LOG2 EXP2
64 Bit Summing Math Operations
ACC64 += <op1> <instr> <op2>	acc64 += R0 macrr R1 acc64 += R8 machri -0.7	Use '+=' or '=' assignment operator Supported instructions MACRR MACRI MACRD MACID MACHRR MACHRI MACHRD MACHID Inferred macr machr
Conditional Branching
IF <cr> <cond> [GOTO] <label>	if r7 >=0 goto mylabel if acc32 neg mylabel if r0 nz goto mylabel	GOTO keyword is optional Must have blanks around condition, not r4>=0 Supported conditions and [synonyms] =0 [z] [jz] <>0 [nz] [jnz] >=0 [gez] [jgez] <0 [neg] [jneg] !=acc32.sign [zc] [jzc]	Generates instructions jz jnz jgez jneg jzc
JMP <label> GOTO <label>	goto mylabel	Unconditional branch. JMP and GOTO are synonyms.