Synth Explorer latest (d4dab3def346)

Automatically built from main commit d4dab3d. This download matches the latest website source.

Synth Explorer local-v0.1.0

What's Changed

• Bound schematic node detail DOM by @cachanova in #138
• Cache equivalent ELK layout geometry by @cachanova in #139
• Polish Vivado schematic primitives and flags by @cachanova in #140
• Reduce ELK work on very large schematics by @cachanova in #141
• Label node details with synthesis tool by @cachanova in #142
• Adapt ELK layout to graph density by @cachanova in #143
• Shrink the logo eye across every branded surface by @cachanova in #146
• Stack primitives from inferred memories by @cachanova in #144
• Map internal declarations to schematic logic by @cachanova in #145
• Group parallel SRL memory lanes by @cachanova in #148
• Harden source provenance cross-probing by @cachanova in #149
• Show clock and reset wiring in focused schematics by @cachanova in #150
• Unify source provenance indexing by @cachanova in #152
• Package Synth Explorer as a downloadable local Chrome app by @cachanova in #151

Full Changelog: vivado-bridge-v0.2.1...local-v0.1.0

Synth Explorer Vivado bridge 0.2.1

What's Changed

• Fix Vivado bridge bundled library preflight by @cachanova in #137

Full Changelog: vivado-bridge-v0.2.0...vivado-bridge-v0.2.1

Synth Explorer Vivado bridge 0.2.0

What's Changed

• docs: FABLE.md GPT-5.6 routing — Sol/Terra/Luna tiers, effort levels, lead-seat rationale by @cachanova in #3
• Deploy Synth Explorer to production by @cachanova in #4
• Add XOR probe logo by @cachanova in #1
• Add source-aware schematic and logical endpoint analysis by @cachanova in #2
• Gate production deployment on verified CI by @cachanova in #17
• Fix four production UI defects found in exploratory testing by @cachanova in #18
• Vector grouping, focus mode, memory handling, probe precision, and schematic polish by @cachanova in #19
• Declutter the flip-flop box label by @cachanova in #20
• Schematic: I/O bus grouping, register name labels, double-click expand by @cachanova in #21
• chore: pin shared agent policy by @cachanova in #22
• Schematic UX fixes: register box, remove focus mode, netlist fallback by @cachanova in #23
• Schematic polish: pin alignment, IO-buffer collapse, stack offset, tagline by @cachanova in #24
• Tidy repo docs for open-source browsing by @cachanova in #25
• Move production/deploy files under deploy/ by @cachanova in #26
• Add a Xilinx target-family selector by @cachanova in #27
• Expose synth_xilinx -retime as a toggle by @cachanova in #28
• Fold Xilinx family/retime into the synthesis-flags string by @cachanova in #29
• Fix directional source sub-schematics by @cachanova in #30
• Add a searchable synthesis-flags menu by @cachanova in #31
• Expand registered output source probes by @cachanova in #32
• Estimate worst-case combinational delay (post-synth timing estimate) by @cachanova in #34
• Link the source repository and refresh project READMEs by @cachanova in #35
• Add Focus full-diagram mode and preserve register edges by @cachanova in #37
• Surface estimated timing in the Overview (Tier 0 UI) by @cachanova in #36
• Fix LUT graph labels and styling by @cachanova in #39
• Per-target delay presets, speed grade, and a timing retune endpoint by @cachanova in #38
• License Synth Explorer under Apache-2.0 by @cachanova in #40
• Interactive timing model editor (profile, speed grade, coefficients) by @cachanova in #41
• Unify focused and full schematic views by @cachanova in #42
• Target-clock setup-slack readout by @cachanova in #43
• Per-path estimated delay in the Paths tab by @cachanova in #44
• Label ungrouped register bits and remove auto synthesis by @cachanova in #45
• Paths honor the retune model + sort by depth or delay by @cachanova in #46
• Add optional Vivado synthesis backend by @cachanova in #33
• Per-category delay breakdown (launch/logic/routing/setup) by @cachanova in #47
• Expand Vivado targets and controls by @cachanova in #48
• Simplify Vivado targets and expand synthesis flags by @cachanova in #49
• Calibrate the delay model against Vivado + dedicated carry routing by @cachanova in #51
• Rework examples as parameterized RTL modules by @cachanova in #50
• Update shared agent policy by @cachanova in #54
• Make graph navigation accessible and debounce source probes by @cachanova in #55
• Fix frontend lint warnings by @cachanova in #59
• Fix analysis and rendering performance hotspots by @cachanova in #56
• Stabilize graph focus and additive layout by @cachanova in #57
• Calibration harness, per-family speed grades, and an honest accuracy claim by @cachanova in #58
• feat(timing): surface Vivado's own report_timing beside the estimate by @cachanova in #52
• fix(timing): stop timing the clock tree as a data path by @cachanova in #53
• Correct the carry-routing claim: the free-into-carry rule is right by @cachanova in #61
• Update GitHub Actions to Node 24 runtimes by @cachanova in #63
• Remove compare tab and simplify controls by @cachanova in #64
• calibrate: sweep extra synth_xilinx flags, record LUT count and per-class depths by @cachanova in #65
• Default synth_xilinx to -nowidelut for all families by @cachanova in #67
• Retheme UI to Graphite: neutral dark palette, underline tabs by @cachanova in #69
• calibration: time the Yosys netlist with Vivado over EDIF by @cachanova in #70
• Fix three provenance scanner bugs in case/assign LHS handling by @cachanova in #68
• Persist synthesized designs across restarts by @cachanova in #66
• Refit Xilinx delay presets against Vivado timing our own netlists by @cachanova in #71
• Make -nowidelut a visible client default instead of a hidden server one by @cachanova in #72
• Rebrand logo to XNOR-fish mark with teal accent and bubble loader by @cachanova in #73
• Non-Xilinx timing presets from measured open data, PDK profiles, and no absolute estimate in rtl mode by @cachanova in #74
• Add light mode and selectable color themes via a settings menu by @cachanova in #78
• LUT-map narrow arithmetic via a visible -narrowcarry flag (default 8) by @cachanova in #75
• Surface the brand bubble loader across every in-flight state by @cachanova in #76
• Make focus mode own schematic relayouts by @cachanova in #77
• Offer only mode-appropriate delay profiles by @cachanova in #80
• Keep long stat values inside cards by @cachanova in #79
• Tighten the default-flag explanations to one line each by @cachanova in #82
• Match editor colors to the selected theme by @cachanova in #81
• Measure UltraScale+ wide-mux delay by @cachanova in #86
• Calibrate Lattice timing estimates end to end by @cachanova in #87
• Price ASIC timing by gate category by @cachanova in #83
• Show all bounded endpoints and paths by @cachanova in #88
• Remove repeated depth disclaimers from tabs by @cachanova in #89
• Timing honesty: delay-true paths, delay-ranked sort, no notional numbers by @cachanova in #90
• Flag notes: name the custom flag, explain the real ones by @cachanova in #84
• Route flip-flop controls to their schematic pins by @cachanova in #92
• One resolved TimingView per design: locked profiles, honest controls by @cachanova in #98
• Move source selection into a browser worker by @cachanova in #85
• Highlight schematic boundary nets by @cachanova in #100
• Run Synth Explorer entirely in the browser by @cachanova in #101
• Make Vercel npm 10 install reproducible by @cachanova in #103
• Synthesize continuously in the bro...