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@cbroschard cbroschard released this 27 Aug 20:55
· 1 commit to main since this release
v0.8.4.6-alpha
db15b8f

v0.8.4.6-alpha

This release focuses heavily on VIC-II accuracy, CPU/VIC timing, stability, media handling, and emulator architecture.

A major part of the work over the past two weeks has been moving additional VIC-II behavior away from scanline-level approximations and toward more accurate cycle-based execution.

Highlights

  • Major VIC-II fetch and graphics pipeline improvements
  • Fixed significant graphics issues in RoboCop 3
  • Fixed a graphics regression in Dig Dug
  • Resolved an Action Biker raster IRQ regression
  • Improved sprite pointer, DMA, MC/MCBASE, and Y-expansion handling
  • Improved bad-line and background graphics fetch sequencing
  • Improved CPU/VIC bus arbitration and interrupt timing
  • Corrected NMOS 6510 KIL/JAM behavior in the micro-op CPU path
  • Improved repeated T64/datasette loading
  • Hardened emulator shutdown against intermittent access violations
  • Continued save-state compatibility and versioning improvements
  • Continued SID oscillator/state architecture work
  • Expanded VIC-II and CPU diagnostics in the built-in monitor
  • Fixed regression from last release where old palette was loaded during SDL 2 to 3 upgrade

VIC-II Improvements

The VIC-II execution pipeline received substantial timing and architecture work.

Graphics Fetch Pipeline

Background graphics accesses are now handled during the VIC fetch phase rather than being coupled to later rendering activity.

Graphics sequencer advancement now occurs after the appropriate graphics memory access.

This provides more accurate ordering between:

  • VIC memory accesses
  • CPU bus availability
  • graphics sequencing
  • sprite activity
  • register changes

Sprite Fetch Timing

Sprite pointer fetching has been moved to the correct fetch-slot timing.

This fixed cases where sprite data could be fetched using stale or incorrect pointer values.

Additional sprite-related work includes:

  • Sprite DMA sequencing improvements
  • MC/MCBASE timing improvements
  • Y-expansion behavior refinements
  • Sprite pointer fetch timing corrections
  • Improved sprite state diagnostics

Bad-Line and Register Timing

Additional work was completed around:

  • Bad-line fetch sequencing
  • D011 timing
  • D016 timing
  • D018 timing
  • mid-frame VIC register changes
  • graphics sequencer state
  • raster event tracking

Compatibility Fixes

RoboCop 3

Fixed major graphics corruption affecting multiple RoboCop 3 screens.

The issue was traced primarily to the ordering of:

  • background graphics fetches
  • sprite pointer fetches
  • graphics sequencer advancement

Sprite pointers are now fetched at the proper VIC fetch-slot boundary and background graphics accesses occur during the appropriate fetch phase.

Dig Dug

Fixed a graphics regression uncovered during VIC-II sequencing changes.

Action Biker

Resolved a raster IRQ comparator regression that caused screen flashing.

Eye of the Beholder

Corrected micro-op CPU behavior when encountering NMOS 6502/6510 KIL/JAM instructions.

Additional graphics compatibility work for this title remains ongoing.

CPU / 6510

Continued improvements to the cycle-accurate micro-op CPU implementation.

Changes include work around:

  • interrupt recognition timing
  • RTI behavior
  • RDY/AEC stalls
  • CPU/VIC arbitration
  • stalled instruction fetches
  • undocumented instructions
  • KIL/JAM behavior
  • cycle-level tracing

SID

Continued restructuring of the SID implementation.

Work in this release focuses on keeping behavior that is common to all SID revisions separate from future model-specific behavior.

Additional work was also completed around SID save-state versioning and oscillator state handling.

Save States

Continued improvements to the save state architecture. Any existing save states will not work with this release due to the changes for the SID.

Media / Datasette

Improved repeated T64 loading.

Previously, attaching another T64 while one was already active could overwrite machine state or leave the C64 in an unsuitable state for launching the next program.

Media switching now performs a safer reset/load transition and avoids the emulator freeze encountered during repeated T64 attachment.

Added T64 index selection if there is more than one program to the UI.

Updated UI to show various live statics when using the datasette.

Stability

Improved emulator shutdown and component teardown.

Shutdown now more deliberately disconnects callbacks and cross-component references before components are destroyed.

Areas updated include:

  • video callbacks
  • audio shutdown
  • monitor/debug connections
  • virtual modem devices
  • user-port devices
  • trace managers
  • cartridge references
  • chipset references

Run-loop changes also eliminated a reproducible access violation encountered when closing the emulator window introduced in the last release.

Cartridge / Expansion Hardware

Continued cartridge and expansion-device cleanup.

Work includes:

  • mapper reset-state auditing
  • continued EasyFlash state review
  • improved cartridge initialization/reset behavior
  • moved REU menu from the system menu to the peripheral menu

Monitor / Diagnostics

Expanded the built-in machine-language monitor to assist with cycle-sensitive debugging.

VIC diagnostics now provide increasingly detailed visibility into:

  • raster and cycle position
  • VIC registers
  • color registers
  • VIC memory banks
  • screen/character/bitmap locations
  • sprite DMA state
  • sprite MC/MCBASE state
  • sprite pointers
  • register-write events
  • raster event summaries
  • raster IRQ state

CPU tracing and execution diagnostics were also expanded.

Monitor formatting was reviewed to prevent persistent C++ stream settings such as std::setfill() from leaking into later commands, especially help output.

Internal Cleanup

Additional cleanup was completed across the CPU, VIC-II, machine lifecycle, and component interfaces.

This included:

  • dead-code removal
  • reducing public API surface
  • removing obsolete timing paths
  • separating fetch/render responsibilities
  • improving component ownership
  • improving shutdown boundaries
  • consolidating machine wiring
  • simplifying future timing work

Known Areas Still Under Development

This remains an alpha release. Active accuracy work continues in areas including:

  • VIC-II sprite timing
  • raster IRQ edge cases
  • PAL/NTSC timing differences
  • mid-scanline register writes
  • multicolor graphics edge cases
  • CPU/VIC arbitration
  • SID model-specific behavior
  • cartridge and expansion hardware accuracy

Summary

v0.8.4.6-alpha is primarily an accuracy and stability release.

The most significant improvements are in VIC-II memory-fetch sequencing, sprite timing, CPU/VIC interaction, media handling, save-state robustness, and emulator shutdown stability.

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