inline_memory: optimize mem_is_zero for riscv using RISC-V Vector (RVV) intrinsics #65354
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@tchaikov Hi, could you please help review the RISC-V part? Thanks. |
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The current commit message uses "v intrinsic" which might be unclear to developers not deeply familiar with RISC-V terminology. Consider expanding this to be more descriptive:
Instead of: "v intrinsic", please consider: "RISC-V Vector (RVV) intrinsics" .
also, please use the imperative mood in the commit title. see https://github.com/ceph/ceph/blob/main/SubmittingPatches.rst#commit-title
sunyuechi
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…V) intrinsics
On the bpi-f3 device, the output of running
ctest -V -R unittest_memory is as follows:
size | default | v intrinsic
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1024 | 332ms | 92ms
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2048 | 657ms | 186ms
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4096 | 1290ms | 366ms
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8192 | 2572ms | 733ms
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65536 | 24836ms | 10004ms
Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
tchaikov
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tchaikov
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my only concern is that this might break riscv installations where the RVV instruction set is not available while the building host does support it.
@sunyuechi is it safe to assume its existence on mainstream RISC CPUs?
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@tchaikov It should not assume that the CPU supports RVV; however, since |
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| #elif defined(__riscv_v_intrinsic) |
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OK, shouldn't affect other architectures.
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@rzarzynski @tchaikov Could you please help merge it? Thank you. |
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Optimize mem_is_zero using RISC-V V extension instructions.
On the bpi-f3 device, the output of running
ctest -V -R unittest_memoryis as follows:Checklist
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