Skip to content
View chellajeevanajyothi-maker's full-sized avatar

Block or report chellajeevanajyothi-maker

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. VLSI-design.sarvagna1 VLSI-design.sarvagna1 Public

    cache memory with LRU replacement-AXI lite slave interface for memory- 8bit pipelined ALU simulation-,barel shifter using verilog-priority encoder 8 to 3-design ,synthesize a 2-input 1-select multi…

  2. certificates certificates Public

    project certificates

  3. NIELIT-curriculum NIELIT-curriculum Public

    VLSI verification-lab SOC verification , FPGA architecture

  4. curriculam-SRKIT-LAB curriculam-SRKIT-LAB Public

    SRKIT lab

  5. curriculum-NIELIT-calicut curriculum-NIELIT-calicut Public

    Lab SOC verification-VLSI verification-FPGA architecture-ARM SOC design

  6. FPGA-2 FPGA-2 Public

    FPGA