commit #0b7fef44f removes SBT, requires mill #3483

gsomlo · 2023-09-12T20:41:02Z

Type of issue: bug report

Impact: unknown

If the current behavior is a bug, please provide the steps to reproduce the problem:

make ... -C rocket-chip/vsim verilog CONFIG=<model> fails (is no longer self-contained)

What is the current behavior?

...
/bin/bash: line 1: mill: command not found
...

What is the expected behavior?

make command successfully builds inside self-contained rocket-chip + submodules repo tree.

Please tell us about your environment:

- version: 50adbdb3e
- OS: `Linux 6.4.12-200.fc38.x86_64 #1 SMP PREEMPT_DYNAMIC Wed Aug 23 17:46:49 UTC 2023 x86_64 GNU/Linux`

What is the use case for changing the behavior?

I'm not sure if disabling SBT in favor of mill was deliberate or accidental (I'm aware the commit was lurking around in the dev branch for a while now :) ). However, if it's deliberate, it'd be nice if mill were included as a submodule or somehow otherwise made a "transparent" part of the build process within the rocket-chip repo...

The text was updated successfully, but these errors were encountered:

gsomlo · 2023-09-12T21:00:21Z

Also, if I install and configure mill like so:

git clone https://github.com/com-lihaoyi/mill
mill/mill --help  # downloads to ${HOME}/.cache/mill/download/0.11.0
export MILL=${HOME}/.cache/mill/download/0.11.0

then

make ... -C rocket-chip/vsim verilog CONFIG=...

I get an error:

make: Entering directory '~/rocket-chip/vsim'
cd ~/rocket-chip && ~/.cache/mill/download/0.11.0 rocketchip.assembly
[build.sc] [44/49] cliImports 
Cannot resolve rocketchip.assembly. Try `mill resolve rocketchip._` to see what's available.
make: *** [~/rocket-chip/Makefrag:47: ~/rocket-chip/out/rocketchip/assembly.dest/out.jar] Error 1
make: Leaving directory '~/rocket-chip/vsim'

This did not use to happen a few months ago when I (accidentally :) ) tested the dev branch and figured out how to use mill...

n-kremeris · 2023-09-13T13:01:08Z

I am facing the same issue as @gsomlo.

I have also tried using different versions of mill (e.g. "DEFAULT_MILL_VERSION=0.11.2 make" in rocket-chip/emulator), while still observing the same error no matter which version I used.
"Cannot resolve rocketchip.assembly. Try mill resolve rocketchip._ to see what's available. "

commit 50adbdb

HakamAtassi · 2023-09-16T17:35:18Z

Me as well. I have reverted to commit [eee99e8] and things seem to be going more smoothly, so far.

Nevermind, I seem to be having issues across the board. I'm unable to build rocketchip.

jerryz123 · 2023-09-19T05:34:42Z

Unfortunately, the standalone rocket-chip build support has been deprecated and removed, due to lack of developer resources to maintain that feature. To build and test SoCs with rocket-chip, users should seek out SoC frameworks.

Two options include :

https://github.com/ucb-bar/chipyard, which provides a comprehensive mono-repo for hardware design
https://github.com/chipsalliance/playground, which uses mill+nix for a lighter-weight, and more modular development environment

gsomlo · 2023-09-20T00:43:15Z

On Mon, Sep 18, 2023 at 10:34:54PM -0700, Jerry Zhao wrote: Unfortunately, the standalone rocket-chip build support has been deprecated and removed, due to lack of developer resources

While I find that extremely disappointing, I fully understand about limited resources available for maintenance. My own ToDo list has been known to grow faster than I can address tasks currently on it. In fact, based on this decision, one such high-priority item: "learn enough Chisel to understand (and maybe eventually contribute to) Rocket" can now be safely scratched off that list, freeing up valuable time for other things I'm supposed to be working on... :D

Given the upstream chipsallliance/rocket-chip decision to remove support for independent builds (i.e., `make verilog`, see github.com/chipsalliance/rocket-chip/issues/3483#issuecomment-1724857339), check out the last commit before the breaking merge (#4f197707e). Similarly, check out the version of the L2 cache current at around the same time (#51d400b) to avoid further upstream drift. NOTE: Unless upstream reconsiders, this is likely the *LAST* version of the Rocket Chip to be supported for inclusion in LiteX! Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

n-kremeris · 2023-09-20T09:20:34Z

Unfortunately, the standalone rocket-chip build support has been deprecated and removed, due to lack of developer resources to maintain that feature. To build and test SoCs with rocket-chip, users should seek out SoC frameworks.

Two options include :

https://github.com/ucb-bar/chipyard, which provides a comprehensive mono-repo for hardware design

https://github.com/chipsalliance/playground, which uses mill+nix for a lighter-weight, and more modular development environment

Hi Jerry and thanks for the info. Could you elaborate a little bit about what exactly is removed? If i understand correctly, "removal of standalone build support" is actually more like the build configs from sbt haven't been moved to mill?

I'm currently ramping up on scala/chisel with some mill on the side, so unless there are some standalone-build breaking changes in the chisel code itself, I might try and port the standalone build from sbt to mill.

jerryz123 · 2023-09-20T17:56:50Z

If i understand correctly, "removal of standalone build support" is actually more like the build configs from sbt haven't been moved to mill?

The SBT build files, and the Makefile flow which relied on that, no longer works.

It is still entirely possible to emit verilog from this repo using mill, unfortunately the README hasn't caught up with these changes. @sequencer can you or someone on your end update the README?

I might try and port the standalone build from sbt to mill.

To be clear, the part that is broken is the standalone makefile-to-verilog flow. This would be worth bringing up to date.

jerryz123 · 2023-09-20T18:37:49Z

@gsomlo @n-kremeris , I see that you guys are looking at updating rocket-chip support within Litex.

We are focusing efforts towards making rocket-chip usable as a library, rather than a standalone repository. Maintaining whatever is necessary to make rocket-chip-Litex integration easy is work I, along with the other active maintainers, would be willing to do.

gsomlo · 2023-09-20T18:55:16Z

@jerryz123 Thanks much for the clarification! Short of using SBT, I would be perfectly OK going with a mill-based process similar to what I outlined in #3483 (comment) (above).

However, the steps shown there don't seem to be working at the moment either (I'm getting Cannot resolve rocketchip.assembly. Try ``mill resolve rocketchip._`` to see what's available.). If whatever causes that error could be fixed (whether by providing an updated set of steps for using mill to make verilog, or by fixing whatever's currently broken within the rocket-chip repo to to get make verilog working again[1] when using mill), that would be a perfectly fair way to move forward :)

[1]: the steps shown in #3483 (comment) did work on the dev branch of rocket-chip somewhere around the July-August time frame, but aren't working (using mill) right now on the master branch.

Thanks again,
--G

jerryz123 · 2023-09-20T18:59:00Z

Try mill rocketchip[3.6.0].assembly

I will try to find some time to restore the make verilog flow. I think make sim will be no longer be supported going forwards.

gsomlo · 2023-09-20T19:15:07Z

@jerryz123 -- looks like #3489 is the solution. Any idea when it might land in master (currently it has only been applied to the dev branch).

jerryz123 · 2023-09-20T19:20:06Z

I opened the backport PR. It should get merged in as soon as the tests run.

Some developers want the dev branch to aggressively pursue newer Chisel versions, which could break backwards-compatibility for many projects which cannot bump Chisel versions so aggressively. Thus, we've adopted a backport flow, where PRs are made against dev, then backported to master.

sequencer · 2023-09-21T07:19:27Z

Sorry for the late reply. I'll update the readme later this week. I'm currently out of the office.
For the vcs simulation flow, I'd like to provide some base BFM infrastructure in the future and use verilog+dpi TB to support both verilator and vcs.

jerryz123 · 2023-09-21T17:30:24Z

#3494 updates the Makefile + README.

More importantly, the backport PRs seem to get stuck in CI somewhere... which is blocking commits to master

jerryz123 · 2023-09-26T18:54:28Z

We've updated the README + makefile in master so that a simple make verilog flow now works.

jerryz123 · 2023-09-26T18:57:42Z

I jumped the gun, I'm getting confused with all these PRs. #3494 will go in imminently, and once that goes in, the backport will fix up master. This should happen within a few hours of this post.

gsomlo · 2023-09-30T16:57:44Z

so, I tried (against commit e377336, current tip of master branch):

export MILL=${HOME}/.cache/mill/download/0.11.0
make RISCV=${HOME}/RISCV -C rocket-chip verilog CONFIG=freechips.rocketchip.system.TinyConfig

and got (after a fair amount of work happened):

freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.TinyConfig].mfccompiler.compile 
1 targets failed
emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.TinyConfig].mfccompiler.compile java.io.IOException: Cannot run program "firtool" (in directory "/home/somlo/LITEX/pythondata-cpu-rocket/pythondata_cpu_rocket/verilog/rocket-chip/out/emulator/freechips.rocketchip.system.TestHarness/freechips.rocketchip.system.TinyConfig/mfccompiler/compile.dest"): error=2, No such file or directory
    java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1143)
    java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1073)
    os.proc.proc$lzycompute$1(ProcessOps.scala:134)
    os.proc.proc$1(ProcessOps.scala:128)
    os.proc.spawn(ProcessOps.scala:141)
    os.proc.call(ProcessOps.scala:80)
    millbuild.build$Emulator$mfccompiler$.$anonfun$compile$2(build.sc:152)
    mill.define.Task$TraverseCtx.evaluate(Task.scala:71)
java.io.IOException: error=2, No such file or directory
    java.base/java.lang.ProcessImpl.forkAndExec(Native Method)
    java.base/java.lang.ProcessImpl.<init>(ProcessImpl.java:314)
    java.base/java.lang.ProcessImpl.start(ProcessImpl.java:244)
    java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1110)
    java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1073)
    os.proc.proc$lzycompute$1(ProcessOps.scala:134)
    os.proc.proc$1(ProcessOps.scala:128)
    os.proc.spawn(ProcessOps.scala:141)
    os.proc.call(ProcessOps.scala:80)
    millbuild.build$Emulator$mfccompiler$.$anonfun$compile$2(build.sc:152)
    mill.define.Task$TraverseCtx.evaluate(Task.scala:71)
make: *** [Makefile:11: verilog

I then tried one of my customized LiteX configurations:

cat >> rocket-chip/src/main/scala/subsystem/Configs.scala <<- "EOT"

	class WithMemoryDataBits(dataBits: Int) extends Config((site, here, up) => {
	  case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
	})

	class WithLitexMemPort extends Config((site, here, up) => {
	  case ExtMem => Some(MemoryPortParams(MasterPortParams(
	                      base = x"8000_0000",
	                      size = x"8000_0000",
	                      beatBytes = site(MemoryBusKey).beatBytes,
	                      idBits = 4), 1))
	})

	class WithLitexMMIOPort extends Config((site, here, up) => {
	  case ExtBus => Some(MasterPortParams(
	                      base = x"1000_0000",
	                      size = x"7000_0000",
	                      beatBytes = site(SystemBusKey).beatBytes,
	                      idBits = 4))
	})

	class WithLitexSlavePort extends Config((site, here, up) => {
	  case ExtIn  => Some(SlavePortParams(
	                      beatBytes = site(SystemBusKey).beatBytes,
	                      idBits = 8,
	                      sourceBits = 4))
	})
	EOT

# Configure port settings, ensure sufficient external IRQs:
cat >> rocket-chip/src/main/scala/system/Configs.scala <<- "EOT"

	class BaseLitexConfig extends Config(
	  new WithLitexMemPort() ++
	  new WithLitexMMIOPort() ++
	  new WithLitexSlavePort ++
	  new WithNExtTopInterrupts(8) ++
	  new WithCoherentBusTopology ++
	  new BaseConfig
	)

	class WithLitexHextConfig extends Config(
	  new WithHypervisor ++
	  new WithBitManip ++ new WithBitManipCrypto ++
	  new WithCryptoNIST ++ new WithCryptoSM
	)

        class LitexConfig_linux_8_2 extends Config(
          new WithNBigCores(8) ++
          new WithMemoryDataBits(128) ++
          new BaseLitexConfig
        )
	EOT

make RISCV=${HOME}/RISCV -C rocket-chip verilog CONFIG=freechips.rocketchip.system.LitexConfig_linux_8_2

and got (in fairly short order):

[build.sc] [44/49] cliImports 
Cannot resolve emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.LitexConfig_linux_8_2].mfccompiler.compile. Try `mill resolve emulator._` to see what's available.
make: *** [Makefile:11: verilog] Error 1

I'm guessing there's still something missing before one could successfully do a make verilog build...

Thanks again for looking into it!

n-kremeris · 2023-10-03T10:50:09Z

@gsomlo
You can download firtool from here: https://github.com/llvm/circt/releases
I managed to complete "make verilog" successfully with the default config now

n-kremeris · 2023-10-03T14:00:53Z

To generate the litex custom config, at least 3 changes must be made from the Rocket side of things:

remove underscores, e.g. LitexConfig_linux_1_1 -> LitexConfigLinux11
add LitexConfigLinux11 into build.sc, eg. ~lines 265-283:
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigLinux11"),
Change DefaultConfig to LitexConfigLinux11 in Makefile

This seems to correctly build the rocketchip with the desired Litex config. I haven't yet looked at what changes must be done to update.sh/pythondata-cpu-rocket

gsomlo · 2023-10-03T14:16:16Z

On Tue, Oct 03, 2023 at 03:50:21AM -0700, Norbert Kremeris wrote: @gsomlo You can download firtool from here

Oh, great! First mill, OK. Now some other rando download -- this is quickly headed for NPM-like levels of dependency hell... :(

seldridge · 2023-10-03T17:47:52Z

Oh, great! First mill, OK. Now some other rando download -- this is
quickly headed for NPM-like levels of dependency hell... :(

😂 That's not just any rando dependency. 😂 That's a much more (~4x conservatively) performant FIRRTL compiler that produces better, more readable Verilog output. 😉

Note that on the Chisel side, we are intending to make this download automatically handled like a normal Java dependency. @jackkoenig has an experimental approach that will download this for you from Maven. It's slightly more complicated than normal as it's a binary dependency and not a Java dependency and this has taken some time to sort out.

sequencer · 2023-10-03T21:56:53Z

In order to resolve the dependency issues(and avoid NPM dependency hell as well), In rocket-chip, I choose these solutions:

for JVM stack-software, use mill for build and dependency management(believe me SBT sucks);
for dependencies that don't provide a release, use mill to build from source: hardfloat, cde, riscv-opcodes
for native dependencies, we use nix to manage them, and make it be able to run in different architecture and distros, (e.g. most user use x86, while I'm using an aarch64-linux, some use Ubuntu, while I'm using Arch). for native dependencies, there are two different parts:

software for elaboration and emulation, e.g. circt, espresso, verilator.
software for test case generation, e.g. riscv-gcc riscv-clang, riscv arch test, riscv tests.

I understand installing nix, and run a daemon for it is not quite straightforward for hardware design users, I aware that, and I'll also try to find some alternative solutions to new users(e.g. provide a docker container and release it)

I hope users understand, we reduces burdens(SBT, legacy Chisel version support, a stable API and a version based backport-flow) since

dependencies are hard to manage, there are different ways to manage, see other project from Google, they even depend on a shared cache. Nix may be hard to understand by new users, but it really save our time.
build system are hard to manage, mill does have some shortages(e.g. absolute path), but it's almost a state of the art comparing to other different build systems.(SiFive even develop their own build system https://github.com/sifive/wake)
We have a limited human resource to manage such a big project. For now only 2 active PhD(I and Jerry) are maintaining it(originally the entire SiFive R&D)

After all, we are still making progress, we may have some breaking change, or even introduce issues that makes some user not happy(like this) in the future, but please understand, our goal for now is improving the development efficiency to make the rocket-chip continue and alive at least.

So for most dependencies/build questions, my only suggestion is:
nix develop -c mill resolve __ and read the build script to see what you can do.

jerryz123 · 2023-10-03T22:00:54Z

2. add LitexConfigLinux11 into build.sc, eg. ~lines 265-283:
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigLinux11"),

@sequencer Is it possible to have mill parse a string for the Config as it was done before? Having to mirror the configs into the build.sc is not ideal

sequencer · 2023-10-03T22:20:48Z

@sequencer Is it possible to have mill parse a string for the Config as it was done before? Having to mirror the configs into the build.sc is not ideal

It's not simple, since, mill find configuration statically, there are two solutions:

provide these configuration from another file, e.g. "config.json", and mill read this file to generate the task graph.(See what I did in chipsalliance/t1 ;p)
parse Scala Config, and automatically generate the task via meta-build feature, which is not a trivial work, and I think we don't have bandwidth for it.

gsomlo · 2023-10-03T23:19:32Z

On Tue, Oct 03, 2023 at 02:57:05PM -0700, Jiuyang Liu wrote: In order to resolve the dependency issues(and avoid NPM dependency hell as well), In rocket-chip, I choose these solutions:

@sequencer, @jerryz123: First off, thank you for your hard work maintaining this project. Last thing I want is to add "negative energy" from the peanut gallery, and sorry if anything I said reads that way... :) As a "downstream consumer" of RocketChip, I (personally) value the ability to trust the output of a build process by keeping a handle on all (most?) of the "moving parts". A large part of that is ability to understand, track, and control the "main" project's dependencies. It makes sense for a project such as Rocket to depend on a few other projects that are also "fast-evolving" in their own right (e.g., Chisel, mill, etc.). But in order to maintain any sort of confidence in the output of a build of the project, as we descend down the tree of dependencies, things should hopefully settle down into "slow-and-stable", i.e. things that might be reasonably packaged for a distro (debian/ubuntu/fedora/etc.) and updated once every few months, if not even less frequently. If the "fast-evolving" nature of the dependency chain is preserved too many layers deep, then we have an "everything everywhere all at once" situation that only one or two developers can reasonably keep a handle on, and anyone else might get lucky to receive a dockerfile of a snapshot of one of the developers' environments, so as to be able to ritually "cargo-cult" a rebuild, but without any chance of any control or understanding of what's going on. I understand the latter scenario is sometimes inevitable, and that's OK, I'm happy to wait for it to stabilize once again. I wish I were enough of a Chisel/Scala ninja to offer some assistance, but that's not (yet) the case... :( Best of luck with your degrees, that should be priority #1! :D Cheers, --Gabriel

n-kremeris · 2023-10-24T10:30:00Z

@jerryz123 @sequencer

We've updated the README + makefile in master so that a simple make verilog flow now works.

Do we have a way to restore the verilator emulator binary build flow too?

sequencer · 2023-10-24T10:46:11Z

Do we have a way to restore the verilator emulator binary build flow too?

I don't think so, you can maintain it on your own, but not in the rocketchip upstream repo.

You can see github action, emulator works fine, It works even on an aarch64 machine, I don't think there is any reason to restore it.

n-kremeris · 2023-10-24T10:51:34Z

You can see github action, emulator works fine, It works even on an aarch64 machine, I don't think there is any reason to restore it.

Hi and thanks for the reply! Please could you explain a little bit more? I looked at the github actions tab, but I'm not sure where to find references to the emulator

sequencer · 2023-10-24T10:53:08Z

try nix develop -c mill runnable-riscv-test[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig,_,_].run to run all test for DefaultConfig

n-kremeris mentioned this issue Sep 19, 2023

RocketChip standalone build support is deprecated upstream, requires use of SoC frameworks litex-hub/linux-on-litex-rocket#35

Closed

gsomlo mentioned this issue Sep 20, 2023

RocketChip with L2 cache - works in litex sim, works on digilent nexys video with cpu-mem-width is 64, breaks with 128 enjoy-digital/litex#1746

Open

jerryz123 closed this as completed Sep 26, 2023

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commit #0b7fef44f removes SBT, requires mill #3483

commit #0b7fef44f removes SBT, requires mill #3483

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commit #0b7fef44f removes SBT, requires mill #3483

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