Bump spec testsuite to 13734f8#5
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Superseded by #9 (latest spec bump) |
chaploud
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- ci.yml: build shared lib + run FFI test suite on Linux/macOS - CLAUDE.md: add FFI test step (#5) to commit gate, merge gate
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May 4, 2026
…ndments (regret triage) New rule `.claude/rules/bug_fix_survey.md` (regret #9, twin-largest): before applying a bug fix, grep for same-class cases. Codifies the D-027 case study (if-then fix landed; if-result for block / loop needed re-application). Complements textbook_survey.md's task-start discipline with bug-fix-time discipline. 5 new lessons under `.dev/lessons/2026-05-04-*.md`: - emit-monolith-cost (regret #1) — 9-module split target for ADR-0021 row 7.5d-b - liveness-stage-extension-debt (regret #2) — frame-based dispatch restructure deferred - adr-0017-merge-blind-spot (regret #3) — ADR-0017 missed CFG join semantics; X19 amend hid the gap - adr-revision-history-misuse (regret #7) — Revision history needs gap/refinement/expansion categorisation - adr-batch-dependency-order (regret #10) — 4-ADR batch (0017-0020) had implicit DAG; propose Dependencies section INDEX.md gets 5 new rows. Two amendments to `.claude/rules/edge_case_testing.md`: - "Fixture-internal workarounds trigger debt entries" (regret #4) - "Test-side byte offsets must be relative" (regret #6) Regret #5 (default value re-changes) → not a rule; covered by liveness-stage-extension-debt lesson + commit message hygiene. Regret #8 (sub-row ROADMAP normalization) → ADR-0022 retrospective will document; not a one-time bookkeeping row. Cf. ADR-0021 + ADR-0022 (retrospective).
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… + refactor + rules cycle Records the session as a single load-bearing artefact, complementing ADR-0021 (operational sub-gate decision) with the broader process lens. Resolves the forward references to ADR-0022 across 6 files (handover.md, 4 lessons, ADR-0021's lineage citations). Triage map for the 10 regrets surfaced at session start: - #1 (emit monolith) → lesson + ADR-0021 row 7.5d-b - #2 (liveness elif chains) → lesson; restructure deferred - #3 (ADR-0017 merge blind-spot) → lesson; ADR re-frame deferred - #4 (fixture workarounds) → edge_case_testing.md amendment - #5 (default-value churn) → lesson + commit-message hygiene - #6 (test byte-offsets) → prologue.zig helper + edge_case_testing.md amendment - #7 (ADR Revision history misuse) → lesson; README convention deferred - #8 (sub-row ROADMAP normalization) → ADR-0022 process improvement § (deferred) - #9 (bug-fix-time survey) → bug_fix_survey.md (NEW rule) - #10 (ADR batch dependency order) → lesson; Dependencies section deferred Out-of-scope items explicitly named (deferred to follow-up cycles): emit.zig 9-module split, ~128-site bulk byte-offset migration, liveness frame restructure, ADR-0017 honest re-framing, .dev/decisions/README.md Dependencies / DAG convention amendment.
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May 5, 2026
…xor) Second chunk of §9.7 / 7.7. emit.zig + inst.zig extensions for i32 binary ALU: add / sub / mul / and / or / xor — 6 op-arms covered via a single emitI32Binary handler. inst.zig new encoders (4 ops, 9 byte-level tests): - encAndRR (opcode 0x21) - encOrRR (opcode 0x09) - encXorRR (opcode 0x31) - encImulRR (2-byte opcode 0x0F 0xAF /r — operand-role inversion vs ADD/SUB: dst is ModR/M.reg, src is r/m, so REX.R extends dst and REX.B extends src — handled via flipped rexForRR call) emit.zig new handler (1 fn, 4 tests): - emitI32Binary: pop rhs + lhs, allocate result vreg, emit MOV dst, lhs ; OP dst, rhs (always-MOV form). Width.d zero-extends to 64 per Wasm i32 semantics. Constraint: dst != rhs. With fresh-vreg-per-op allocation this holds; surfaces as `UnsupportedOp` when regalloc starts reusing slots for in-place updates (peephole that elides the MOV when dst == lhs lands then). Tests: 4 new emit cases asserting full byte streams for add/sub/mul + the AllocationMissing path for stack underflow. The add case verifies the full 26-byte sequence: 55 48 89 E5 prologue 41 BA 07 00 00 00 MOV R10D, #7 (vreg 0) 41 BB 05 00 00 00 MOV R11D, #5 (vreg 1) 44 89 D3 MOV EBX, R10D (lhs lift) 44 01 DB ADD EBX, R11D (rhs add) 89 D8 5D C3 MOV EAX, EBX ; POP RBP ; RET Gates: zig build test / test-all (Mac realworld 55/55 + OrbStack spec_runner 3) / lint --max-warnings 0 / zone_check --gate green on Mac aarch64 + OrbStack Ubuntu x86_64. windowsmini next. Refs: .dev/decisions/0019_x86_64_in_phase7.md, AMD64 Vol.3 IMUL §10.7 (operand-role inversion)
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… M3 ringbuffer (#7) 7-issue cleanup batch の最後 2 件 (調査 + 設計レベルが必要だったもの)。 両 ADR とも survey → セルフレビュー → 反映の 2 サイクルを経た設計 ドキュメントで、実装は別 chunk (7.7-globals / M3-a impl) に委譲。 ADR-0027 (#5 — globals 経路): - 6 主要 Wasm runtime (wasmtime / wasmer / wazero / WAMR / wasm3 / zware) を survey: 100% (6/6) が "globals を vmctx 内に inline embed + [vmctx + offset] で access" を採用。zwasm v1 のみ helper call 路線で ~20 cycle/access の cost penalty を負う異形 - 採用: JitRuntime extern struct を bytes 48-60 で拡張 (globals_base [*]const Value + globals_count u32) - ARM64: X23 を 6 番目の callee-saved invariant として予約 (AAPCS64 callee-saved 10 本のうち 6 本予約 → 4 本残り) - x86_64: ADR-0026 の reload-from-runtime-ptr pattern を踏襲 - ARM64 emit は LDR Rd, [X23, Ridx, LSL #4] (register-offset) を採用、imm12 制限を bypass (~256 globals 上限を回避) - Alternatives B (vtable) / C (VMOffsets) / D (helper call) 全て客観的根拠で reject - ADR-0017 / 0018 / 0026 への amendment 行は 7.7-globals 実装 commit 時に追加 (queue 化) ADR-0028 (#7 — Diagnostic M3 trace ringbuffer 前倒し): - ADR-0016 の M3 phasing を amend: "Phase 7 close 後に再評価" → "7.8 spec gate 着手前に M3-a を land" に方針変更 - 動機: bounds-check #1 fix (commit fe42735) が trace あれば instant に診断可能だった事例 + v1 W54 postmortem (2-3 days → 30 min の診断時間短縮実績) - 設計: 8-byte packed TraceEntry (timestamp / category / event / payload×2) × 32 entries per-thread ring buffer (256 byte / thread) - Categories: jit / regir / regalloc / bounds / trap / exec - Compile-time gate (-Dtrace-ringbuffer) で release zero overhead 維持 (ROADMAP §A12 整合) - Phasing: M3-a (bounds + trap, Phase 7 内) → M3-b (regalloc + jit, Phase 7 close 前) → M3-c (regir + exec, Phase 8+) - Trap stub から drain helper call で caller-saved registers が破壊される旨明記 (post-trap GP register dump は信頼不可、 ringbuffer event sequence のみが canonical audit trail) - D-022 の discharge 前提を満たした (M3-a 実装時に flip) - ADR-0016 への Revision history 追記は M3-a 実装 commit に queue Self-review: code-reviewer subagent を post-design phase に投入。 ADR-0027 で ARM64 callee-saved 計算誤り (X0-X18 caller-saved を 含めていた) を critical 指摘 → 修正 (10 本中 6 本予約 → 4 本残り に正確化)。ADR-0028 で trap-time register state 破壊リスクを critical 指摘 → Negative 節に追記。SHA カラムは `<backfill>` に 統一 (README.md 規律準拠)。 実装は別 chunk: 7.7-globals (ADR-0027 implementation) と M3-a (ADR-0028 implementation) は本 commit には含まない。各実装時に それぞれ ADR-0017 / 0018 / 0026 / 0016 の Revision history 追記 を行う前提。 Refs: ADR-0016, ADR-0017, ADR-0018, ADR-0026, D-021, D-022, ROADMAP §1, §2 P3/P5, §4, §11, §A12, private/notes/ (informal cross-runtime survey notes)
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Lands the i32 sub-scope of ADR-0027 (JitRuntime globals_base
extension): `global.get` / `global.set` end-to-end through both
ARM64 + x86_64 JIT pipelines, with integration test proving the
JitRuntime.globals_base round-trip works through callI32NoArgs.
i64 / f32 / f64 globals are out of scope (next chunk; depends on
existing i64/FP infrastructure that hasn't all landed yet).
src/engine/codegen/shared/jit_abi.zig:
- JitRuntime extern struct extended (head_size 48 → 64):
+ `globals_base: [*]Value` at byte offset 48
+ `globals_count: u32` at byte offset 56 (+ _pad2)
- New offset constants: globals_base_off=48, globals_count_off=56
- Comptime alignment guards extended (8-aligned ptr, 4-aligned u32)
- Existing `head_size = 48` test → `head_size = 64`
ARM64 (per ADR-0027 ARM64 path):
- abi.zig: `globals_base_save_gpr: Xn = 23` reservation;
reserved_invariant_gprs 6 → 7 regs (X19, X23..X28);
allocatable_callee_saved_gprs 4 → 3 regs (X20..X22);
allocatable pool 9 → 8 regs total
- emit.zig prologue: prescan for `global.get` / `global.set`
presence; conditionally emit `LDR X23, [X0, #globals_base_off]`
AFTER the existing 5 LDRs and BEFORE the X19 MOV. Functions
without globals keep the pre-ADR-0027 prologue (zero churn for
existing tests)
- op_globals.zig (new, Zone 2): i32 emitI32GlobalGet (LDR W from
[X23 + idx*8]) + emitI32GlobalSet (STR W to [X23 + idx*8])
- dispatch arm in emit.zig: routes `.global.get` / `.global.set`
to op_globals handlers
- 2 emit-level tests (get + set with explicit byte-sequence
assertion at body+4 / body+8 offsets)
x86_64 (per ADR-0026 reload-from-runtime-ptr pattern):
- inst.zig: 2 new encoders + 4 byte-level tests
+ encMovR32FromMemDisp32 (opcode 0x8B without REX.W)
+ encStoreR32MemDisp32 (opcode 0x89 without REX.W)
- emit.zig: emitI32GlobalGet / emitI32GlobalSet handlers
emit `MOV RAX, [R15+globals_base_off=48]; MOV r/m32, [RAX+
idx*8]`. Mirrors the memory-op reload pattern exactly,
validating ADR-0026's abstraction
- prescan extended: globals access also triggers
uses_runtime_ptr (R15 prologue load required)
- 3 emit-level tests (get / set explicit byte assertions +
AllocationMissing on stack underflow)
Integration test (src/engine/codegen/shared/entry.zig):
- End-to-end JIT execution: `(i32.const 7) (global.set 0)
(global.get 0) end` → returns 7 via callI32NoArgs;
asserts globals[0] was actually overwritten and globals[1]
untouched (proves both set + get traverse the JitRuntime
pointer correctly)
JitRuntime construction sites updated (5 callers): runner.zig +
codegen/shared/{entry,compile}.zig — added .globals_base =
undefined / .globals_count = 0 for the existing zero-globals
test paths (backward-compat).
ADR Revision history backfilled (4 ADRs):
- ADR-0017: JitRuntime layout extension documented
- ADR-0018: ARM64 reserved set 6→7 documented
- ADR-0026: first non-memory consumer (validates the
reload-from-runtime-ptr generalisation)
- ADR-0027: implementation row added with stride correction
(per-Value = 8 bytes, not the 16 the initial Decision text
assumed from wasmtime's SIMD-aligned convention)
Self-review: pre-design phase done at ADR-0027 起草時
(industry survey 6/6 runtimes, ARM64 callee-saved 計算誤り
critical 反映)。本 commit は実装フェーズで scope 限定 (i32 only)、
両 backend integration test が end-to-end 動作確認、handover の
chunk progress table も sync。
Three-host gate: Mac aarch64 (test + test-all + lint +
test-edge-cases all green) + OrbStack Ubuntu x86_64 (test-all)
+ windowsmini SSH (test-all) all pass。
Subsequent: next chunk = 7.7-wrap (i32.wrap_i64 + i64.extend);
post-7.7 deferred: globals i64/FP, M3-a-2 trap stub write.
Refs: ADR-0017 (JitRuntime ABI extension), ADR-0018 (ARM64
register reservation amend), ADR-0026 (x86_64 invariant
strategy validates first non-memory consumer), ADR-0027
(globals decision; #5 of 7-issue cleanup batch fully closed),
ROADMAP §1 §2 P3/P5, edge_case_testing.md
chaploud
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May 17, 2026
Adds permanent diagnostic infra per `.claude/rules/hypothesis_enumeration.md` step-4 (permanent diagnostic primitive per multi-cycle bug): - `host_import_stub_call_count` + `host_import_stub_last_trap_flag` module-globals; incremented per `hostImportTrapStub` invocation to localise the trap source on cross-module-import fixtures. - `printCallTrap` FAIL line emits `[stubs=N last_tf=M]` tail. - Counters reset per assert dispatch (pairs with D-129 `pending_host_import_skip` reset pattern). γ-4 stays STRICT in this commit (Mac+ubuntunote `test-all` EXIT=0). The relax probe (locally toggled, NOT committed) confirms 1 fail on Mac arm64: `imports: call print64(i64:24): Trap [stubs=5 last_tf=0]`. Interpretation: print64 body chains 1 cross-module `$i64->i64` call (no stub) + 5 spectest no-op stubs + 1 `call_indirect` (would be stub fire #6). Counter reads `stubs=5` → trap fires between stub return #5 and call_indirect's BLR. Window contains only call_indirect's prologue (bounds + sig fixups). Bounds check trivially passes (idx 1 < table_size 32). Sig check should pass (both sides canonical(3) per type-section inspection). Yet ONE of those fixups fires — needs per-fixup distinguisher in cycle 3. Refs: - ADR-0068 chunks α/β/γ/γ.2/γ.3 (this is γ.4 diag landing, γ-4 strict held). - D-144 print64 trap row. - hypothesis_enumeration.md (multi-cycle discipline).
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Adds `rt.trap_flag` value to the FAIL line emitted by `printCallTrap` (test/spec/spec_assert_runner_base.zig:412). Pairs with the cycle-2 `[stubs=N last_tf=M]` counters so a cross-module-import-bearing fixture's trap localizes to "before stub N+1" vs "during stub N" vs "JIT code post-call". Local Mac aarch64 observation with γ-4 relax probe applied (reverted before commit per γ-4-strict-pending-D-144-close): FAIL imports: call print64(i64:24): Trap [stubs=5 last_tf=0 tf=1] Localizes the print64 trap to JIT code AFTER stub #5 ($print_f64-2) and BEFORE the call_indirect's BLR — the call_indirect's bounds/sig check or funcptr load sets trap_flag=1. Value=1 is generic (arm64 emit.zig:1444 shares one trap stub for all sources). D-144 row updated with cycle-3 hypothesis refinement: - hypotheses (5)/(6) added: typeidx mismatch / funcptr=0 at table[1] for print_f64 import (despite sibling print32 passing the same elem-segment-populated table at idx 0). - Cycle 4 plan: lldb inspection OR per-fixup-kind W17 marker emit at op_call.zig (permanent infra route). Per `hypothesis_enumeration.md` step-4 discipline (permanent diagnostic infra per multi-cycle debug); `tf=` is the third permanent breadcrumb after cycle-2's stub call counter + last_trap_flag globals.
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…9 partial]
- ADR-0022:195 → `b12f3622` ("ADR-0022 — post-session
retrospective on 2026-05-04 design + refactor + rules cycle";
the file-creation commit per `git log --follow --reverse`).
- ADR-0016:572 → `618ac144` ("ADR-0027 + ADR-0028 — JitRuntime
globals (#5) + Diagnostic M3 ringbuffer (#7)"; the commit
that landed the ADR-0028 amend referenced in the row text).
Backfill ledger:
- 100 placeholders initial.
- 42 mechanical (date-unique) `c9f729ef`.
- 19 Initial-row earliest-commit `3630091b`.
- 9 set-difference `2fd7c25f`.
- 6 narrative-pass `5c75fa0d`.
- 15 narrative-pass `1b19a53f`.
- 2 narrative-pass at this commit.
- Remaining 6: ADR-0017 (4 inline narrative refs) + ADR-0018
(1 inline) + README.md (literal example). All are
paragraph-context-only `SHA: <backfill>` strings, not
Revision-history table rows; each needs surrounding-paragraph
read + commit-message match.
`check_adr_history.sh --gate`: pending 9 → 6; Unknown-SHA: 0.
chaploud
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May 22, 2026
…retarget windowsmini test-all run post-Defender-fix + reboot @ ba68a89 completed without wedge (1692/1721 tests, 37/39 build steps). Previous baseline at HEAD 1b4a5b5 wedged > 120 min mid-corpus. D-028 hypothesis #5 (Defender real-time scan interference at process spawn) CONFIRMED. N=1; need N=5 streak per heisenbug_discharge.md for full discharge. BUT the test-all run also surfaced the real Win64 ABI gap that was hidden by the wedge: panic at entry.zig:1135 callI32f64NoArgs (Class B mixed-class entry helper). The 2026-05-22 F1 fix (0c2474c) used @Panic("D-022") to keep the shared Error narrow per platform_panic_vs_error.md, and the panic tag was reused for grep'ability — but this is a DIFFERENT bug class from the existing D-022 trap-location row. Filed as D-161. D-161 details: - 3 sites: callI32f64NoArgs / callF64i32NoArgs / callF64f32NoArgs (i32→f64 / f64→i32 / f64→f32 Class B mixed-class return) - Impl: Win64 inline-asm thunks mirroring existing arm64+SysV branches at the same callsites (FMOV / movd of XMM0+RAX-class scalars into FuncRet_* extern structs per ADR-0069) - Cohort with D-136 only in "Win64 ABI gap" axis; independent in impl (no SEH bridge needed for entry-helper marshalling) - Autonomous-eligible (no ADR-grade decisions) Handover retargets next chunk to D-161 (autonomous) ahead of W3.b (gated on ADR 0103 flip). The two are independent and can land in either order. D-028 row updated: hypothesis #5 marked CONFIRMED + discharge plan = N=5 streak with D-161-tolerant counting.
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…cycle 87) Per cycle-82 audit §F finding: 12 active blocked-by rows had Last-reviewed > 14 days, simultaneously crossing CHECKS §F.2a narrow-audit threshold. D-058 + D-059 discharged at cycle 85; remaining 11 walked here: | Row | Verification probe | Outcome | |--------|---------------------------------------------------|-------------------| | D-026 | Phase 11 embenchen scope; emcc env-shim runtime | Barrier holds | | D-007 | Phase 11 WASI envv/preopens RunOpts refactor | Barrier holds | | D-010 | rawFreeOwned 3rd-site? 4 sister-uses in runtime.zig (same file) ≠ "third site" | Barrier holds | | D-020 | private/dbg/ count ≥ 5? actual=1 (d132/ only) | Barrier holds | | D-021 | Phase 14 concurrency phase | Barrier holds | | D-022 | ADR-0028 M3-a-2 trap-stub runtime write? unlanded| Barrier holds | | D-028 | Windows IPC heisenbug — hypothesis #5 confirmed | Barrier holds | | D-074 | ADR-0012 §1-§3 tier-provisioning, Phase 11 carrier| Barrier holds | | D-082 | Phase 11 embenchen + Phase 10 GC-touch externref | Barrier holds | | D-148 | Upstream Zig fix for Codeberg #35343 self-hosted x86_64 backend | Barrier holds (no autonomous probe) | | D-075 | ADR-0109 cw v1 dogfooding ≥ 1 minor version | Time-based; not yet | All barriers verified to still hold (Phase 10 still IN-PROGRESS, Phase 11+ deferred barriers can't dissolve; upstream-event barriers can't be probed autonomously). Last-reviewed bumped to 2026-05-28 for all 11; no rows discharged. Side effect: this commit also exercises the newly-wired `check_doc_state --gate` (cycle 86) for the first time on a `.dev/debt.md` touch. Hook ran, passed (debt.md is on the exclusion list per doc_state_marker.md). Cycle-86 wiring confirmed operational.
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Adopt ClojureWasmFromScratch's project-level orphan suppression+cleanup (this repo only had the shared cross-session SessionStart backstop). - .claude/rules/orphan_prevention.md (auto-load **): every backgrounded long-runner must be `timeout`-bounded. WHY is zwasm-specific: the /continue loop backgrounds run_remote_ubuntu.sh/run_remote_windows.sh (3-5min SSH) without waiting (ADR-0076); a parent-session kill orphans them to PID 1, and the pile compounds with Microsoft Defender's continuous .zig-cache/zig-out scan on this Mac (~20% CPU idle) — same real-time-scan interference already root-caused on windowsmini (D-028 #5). - scripts/orphan_guard.sh: sourced prelude — reap prior instance + reap ppid==1 orphaned `ssh <host>` (precise) + re-exec under timeout ${REMOTE_GATE_TIMEOUT:-1800}. - run_remote_{ubuntu,windows}.sh: source the guard (loop invocation UNCHANGED — no LOOP/GATE/SKILL edit, frozen loop contract intact) + ssh ServerAliveInterval/CountMax keepalive (the "timeout does NOT propagate to remote" caveat). Routine per ROADMAP §18 (no §1/§2/§4/§5/§9/§11/§14 deviation; no ADR). Verified: bash -n x3; orphan_guard reap+re-exec+idempotency+arg-passthru unit-tested; stacking-reap kills prior, spares self; check_rule_paths OK.
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…ole (ADR-0202 D5, D-507) Adversarial critique FAIL #5 (CONFIRMED memory-safety regression): the AOT compile path used the default .auto knob → elided .cwasm code, but aot/run.zig binds PLAIN HEAP with no trap region → an oob access reads/ writes past the guest memory silently; reproduced as compile+run oob.cwasm → exit 70 (JIT path cleanly traps exit 1). Enforcement: CompiledWasm.bounds_elided + produceFromCompiledWasm HARD-REFUSES elided (Error.ElidedBoundsNotAotSerializable); compileWasmForAot forces .explicit for every AOT compile; regression test pins it. FAIL #6: the three bespoke-memory spec runners now force .explicit. D-515 tracks the D5 AOT-elision build-out + corpus-under-elision. test-all + lint green.
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…202 D4/D5) — completes D-507 (#133) * feat(codegen): elide memory0 scalar bounds check for guard-page memories (ADR-0202 D4/D5, D-507) Both emit backends gain `bounds_elided`: when memory0 qualifies (i32 × 64 KiB × guarded host) AND the engine knob is `.auto`, memory0 scalar/ atomic accesses drop the inline ADD/CMP/B.HI (x86_64: mem_limit reload + CMP + JA) — the guard-page reservation + fault→trap redirect own oob detection — and force-emit the kind=6 stub as the redirect target. memory64 / bulk / GC-array / SIMD keep explicit checks (SIMD = D-514). Atomic alignment checks are NOT elided. The elision decision uses the SAME memory_backing.qualifies predicate as the runtime backing choice, so elided code only ever binds guarded memory0 (D5 soundness by construction). Engine knob `bounds_checks: .auto|.explicit` (compile.setBoundsChecks, process-global to avoid threading 56 compileWasm callers) — the D-510 differential axis. Any JIT execution now auto-installs the fault handler (entry.invokeAndCheck → signal.ensureInstalled, idempotent, skips when CLI/embedding/spec-runner already installed one) since elided code faults instead of branching. The spec harness backs memory with non-guarded buffers, so it forces .explicit (D-515 tracks running the corpus under elision). New test-oob-elision build step verifies the full production path (guarded memory + elided codegen + guard fault → redirect → trap → exit 1) per-OS. * docs(adr): D-507 phase 3 retrospective — measured elision perf refutes the hypothesis Per-merge bench (arm64) + ADR V-phase note: memory0 scalar bounds-check elision is ~noise on the shootout band (matrix ~1%, base64 ~1.5%, sieve ~4%, fib2 within stddev), NOT the '1.75x floor slice' the ADR Context hypothesised. The check was a pinned-reg CMP + never-taken branch — cheap on OoO; the real 1.75-3.9x gap vs wasmtime is optimising-tier codegen quality (D-513). Elision still ships (correct, code-size win, standard design, D-509-foundational guard-fault infra), but the perf hypothesis is recorded as refuted per the measure-first principle. * fix(aot,spec): close the elided-code + non-guarded-memory soundness hole (ADR-0202 D5, D-507) Adversarial critique FAIL #5 (CONFIRMED memory-safety regression): the AOT compile path used the default .auto knob → elided .cwasm code, but aot/run.zig binds PLAIN HEAP with no trap region → an oob access reads/ writes past the guest memory silently; reproduced as compile+run oob.cwasm → exit 70 (JIT path cleanly traps exit 1). Enforcement: CompiledWasm.bounds_elided + produceFromCompiledWasm HARD-REFUSES elided (Error.ElidedBoundsNotAotSerializable); compileWasmForAot forces .explicit for every AOT compile; regression test pins it. FAIL #6: the three bespoke-memory spec runners now force .explicit. D-515 tracks the D5 AOT-elision build-out + corpus-under-elision. test-all + lint green.
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Automated spec testsuite update. All tests pass.