AMD Rembrandt Memory Controller

[cyring]

Can anyone show me the Memory Controller CoreFreq output of its Zen3+ Rembrandt ?

Because the Ryzen 5 6600H always outputs 4 channels, despite only two DIMMs physically installed. See this issue.

Issue: via SMU, UMC registers reports the same value for group of 4 channels.

Source: Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 11h, Revision B1 Processors Volume 3 of 6 @ AMD tech-docs

For example, 0x050104, 0x150104, 0x250104, 0x350104, which are the addresses of the SDP Control register. Address 0xN50104 where N is the channel number.

Bit 31 SdpInit

BIOS should disable the SDP port for unused UMC channels.

For all these 4 first channels SdpInit is read as enabled rather than for two channels only.

[cyring]

Commit a53fa14