[RISC-V] Preliminary port to the riscv64 architecture

[cyring]

Branch riscv64 portage is made on a QEMU Virtual Machine as described in this Gist

[cyring]

[cyring]

Commit 5c3bc58 brings a mean to read a TSC
We use the same instruction per Core and for the Package.
Base clock is now estimated dynamically,
but no register found for the factory clock which is still hard-coded to 1 GHz (as specified in QEMU)

[cyring]

• mvendorid and marchid based architecture qualification in commit 450189f